Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24187 )
Change subject: x86: Stop clearing RAX for BIST in initCPU.
......................................................................
x86: Stop clearing RAX for BIST in initCPU.
This doesn't actually change any behavior since RAX was being zeroed
anyway, but since we don't and almost certainly never will have a BIST
and the BIST is optional even in real hardware, we can drop it and
simplify initCPU a little further.
This reduces x86's initCPU function to just an invocation of
InitInterrupt's invoke.
Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0
---
M src/arch/x86/utility.cc
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index b00e686..75f242d 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -74,16 +74,7 @@
void
initCPU(ThreadContext *tc, int cpuId)
{
- // This function is essentially performing a reset. The actual INIT
- // interrupt does a subset of this, so we'll piggyback on some of its
- // functionality.
- InitInterrupt init(0);
- init.invoke(tc);
-
- // Set integer register EAX to 0 to indicate that the optional BIST
- // passed. No BIST actually runs, but software may still check this
- // register for errors.
- tc->setIntReg(INTREG_RAX, 0);
+ InitInterrupt(0).invoke(tc);
}
void startupCPU(ThreadContext *tc, int cpuId)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I56b1aae2c1a738ef7ffabcf648dd7d0fb819d4e0
Gerrit-Change-Number: 24187
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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