Hello Tony Gutierrez, Xianwei Zhang,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/29942
to review the following change.
Change subject: arch-gcn3: add support of 64-bit SOPK instruction
......................................................................
arch-gcn3: add support of 64-bit SOPK instruction
s_setreg_imm32_b32 is a 64-bit instruction, using a 32-bit literal
constant. Related functions are added to support decoding the second
dword.
Change-Id: I290f8578f726885c137dbfac3773035f814e0a3a
---
M src/arch/gcn3/insts/op_encodings.cc
M src/arch/gcn3/insts/op_encodings.hh
2 files changed, 43 insertions(+), 4 deletions(-)
diff --git a/src/arch/gcn3/insts/op_encodings.cc
b/src/arch/gcn3/insts/op_encodings.cc
index fe501f2..22d0f48 100644
--- a/src/arch/gcn3/insts/op_encodings.cc
+++ b/src/arch/gcn3/insts/op_encodings.cc
@@ -160,6 +160,14 @@
// copy first instruction DWORD
instData = iFmt[0];
+ if (hasSecondDword(iFmt)) {
+ // copy second instruction DWORD into union
+ extData = ((MachInst)iFmt)[1];
+ _srcLiteral = *reinterpret_cast<uint32_t*>(&iFmt[1]);
+ varSize = 4 + 4;
+ } else {
+ varSize = 4;
+ } // if
} // Inst_SOPK
Inst_SOPK::~Inst_SOPK()
@@ -169,18 +177,43 @@
int
Inst_SOPK::instSize() const
{
- return 4;
+ return varSize;
} // instSize
+ bool
+ Inst_SOPK::hasSecondDword(InFmt_SOPK *iFmt)
+ {
+ /*
+ SOPK can be a 64-bit instruction, i.e., have a second dword:
+ S_SETREG_IMM32_B32 writes some or all of the LSBs of a 32-bit
+ literal constant into a hardware register;
+ the way to detect such special case is to explicitly check the
+ opcode (20/0x14)
+ */
+ if (iFmt->OP == 0x14)
+ return true;
+
+ return false;
+ }
+
+
void
Inst_SOPK::generateDisassembly()
{
std::stringstream dis_stream;
dis_stream << _opcode << " ";
- dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
- dis_stream << "0x" << std::hex << std::setfill('0') <<
std::setw(4)
- << instData.SIMM16;
+ // S_SETREG_IMM32_B32 is a 64-bit instruction, using a
+ // 32-bit literal constant
+ if (instData.OP == 0x14) {
+ dis_stream << "0x" << std::hex << std::setfill('0')
+ << std::setw(8) << extData.imm_u32 << ", ";
+ } else {
+ dis_stream << opSelectorToRegSym(instData.SDST) << ", ";
+ }
+
+ dis_stream << "0x" << std::hex << std::setfill('0') << std::setw(4)
+ << instData.SIMM16;
disassembly = dis_stream.str();
}
diff --git a/src/arch/gcn3/insts/op_encodings.hh
b/src/arch/gcn3/insts/op_encodings.hh
index 22c146a..4f151b9 100644
--- a/src/arch/gcn3/insts/op_encodings.hh
+++ b/src/arch/gcn3/insts/op_encodings.hh
@@ -87,6 +87,12 @@
protected:
// first instruction DWORD
InFmt_SOPK instData;
+ // possible second DWORD
+ InstFormat extData;
+ uint32_t varSize;
+
+ private:
+ bool hasSecondDword(InFmt_SOPK *);
}; // Inst_SOPK
class Inst_SOP1 : public GCN3GPUStaticInst
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I290f8578f726885c137dbfac3773035f814e0a3a
Gerrit-Change-Number: 29942
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez <[email protected]>
Gerrit-Reviewer: Tony Gutierrez <[email protected]>
Gerrit-Reviewer: Xianwei Zhang <[email protected]>
Gerrit-MessageType: newchange
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