Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31415 )
Change subject: mem-ruby: more specialized address to node mapping
......................................................................
mem-ruby: more specialized address to node mapping
Added mapAddressToDownstreamMachine that may be used by the protocols
to map an address to different target donwstream controller of the same
type.
These functions do not use the global mapping provided by the network
and map addresses to one of the controllers specified in the
downstream_destinations parameter.
This change facilitates reusing the same cache state-machine/controllers
to model different levels of the cache hierarchy.
Change-Id: I9a202e9461e0d2f16ed232ff8b60bbde2d15570d
Signed-off-by: Tiago Mück <tiago.m...@arm.com>
---
M src/mem/ruby/common/MachineID.hh
M src/mem/ruby/slicc_interface/AbstractController.cc
M src/mem/ruby/slicc_interface/AbstractController.hh
M src/mem/ruby/slicc_interface/Controller.py
4 files changed, 97 insertions(+), 4 deletions(-)
diff --git a/src/mem/ruby/common/MachineID.hh
b/src/mem/ruby/common/MachineID.hh
index 3ef7b88..3d0827f 100644
--- a/src/mem/ruby/common/MachineID.hh
+++ b/src/mem/ruby/common/MachineID.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2020 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
* All rights reserved.
*
@@ -37,7 +49,7 @@
struct MachineID
{
- MachineID() : type(MachineType_NULL), num(0) { }
+ MachineID() : type(MachineType_NUM), num(0) { }
MachineID(MachineType mach_type, NodeID node_id)
: type(mach_type), num(node_id) { }
@@ -47,6 +59,8 @@
MachineType getType() const { return type; }
NodeID getNum() const { return num; }
+
+ bool isValid() const { return type != MachineType_NUM; }
};
inline std::string
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 9da8727..773ff7c 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017,2019 ARM Limited
+ * Copyright (c) 2017,2019,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -78,6 +78,20 @@
if (getMemReqQueue()) {
getMemReqQueue()->setConsumer(this);
}
+
+ downstreamDestinations.resize();
+ for (auto abs_cntrl : params()->downstream_destinations) {
+ const AddrRangeList &ranges = abs_cntrl->getAddrRanges();
+ if (!ranges.empty()) {
+ MachineID mid = abs_cntrl->getMachineID();
+ AddrMapNode addr_map_node = {
+ .id = mid.getNum(),
+ .ranges = ranges
+ };
+ downstreamAddrMap.emplace(mid.getType(), addr_map_node);
+ downstreamDestinations.add(mid);
+ }
+ }
}
void
@@ -358,6 +372,41 @@
return mach;
}
+MachineID
+AbstractController::mapAddressToDownstreamMachine(Addr addr, MachineType
mtype)
+const
+{
+ std::unordered_multimap<MachineType, AddrMapNode>::const_iterator
+
begin,end;
+ if (mtype == MachineType_NUM) {
+ begin = downstreamAddrMap.begin();
+ end = downstreamAddrMap.end();
+ }
+ else {
+ const auto &matching_ranges = downstreamAddrMap.equal_range(mtype);
+ begin = matching_ranges.first;
+ end = matching_ranges.second;
+ }
+ MachineID mach_id;
+ for (auto it = begin; it != end; it++) {
+ const AddrMapNode &node = it->second;
+ const AddrRangeList &ranges = node.ranges;
+ for (const AddrRange &range: ranges) {
+ if (range.contains(addr)) {
+ fatal_if(mach_id.isValid(),
+ "%s: address %x mapped to multiple controllers\n",
+ name(), addr);
+ mach_id.type = it->first;
+ mach_id.num = node.id;
+ }
+ }
+ }
+ fatal_if(!mach_id.isValid(), "%s: couldn't find mapping for
address %x\n",
+ name(), addr);
+ return mach_id;
+}
+
+
bool
AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt)
{
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh
b/src/mem/ruby/slicc_interface/AbstractController.hh
index 5b43165..81c17d1 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017,2019 ARM Limited
+ * Copyright (c) 2017,2019,2020 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -44,6 +44,7 @@
#include <exception>
#include <iostream>
#include <string>
+#include <unordered_map>
#include "base/addr_range.hh"
#include "base/callback.hh"
@@ -175,6 +176,21 @@
*/
MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
+ /**
+ * Maps an address to the correct dowstream MachineID
+ *
+ * This function uses the local list of possible destinations instead
of
+ * querying the network.
+ *
+ * @param the destination address
+ * @param the type of the destination (optional)
+ * @return the MachineID of the destination
+ */
+ MachineID mapAddressToDownstreamMachine(Addr addr,
+ MachineType mtype = MachineType_NUM)
const;
+
+ const NetDest& allDownstreamDest() const { return
downstreamDestinations; }
+
protected:
//! Profiles original cache requests including PUTs
void profileRequest(const std::string &request);
@@ -273,6 +289,15 @@
private:
/** The address range to which the controller responds on the CPU
side. */
const AddrRangeList addrRanges;
+
+ struct AddrMapNode {
+ NodeID id;
+ AddrRangeList ranges;
+ };
+ std::unordered_multimap<MachineType, AddrMapNode> downstreamAddrMap;
+
+ NetDest downstreamDestinations;
+
};
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/ruby/slicc_interface/Controller.py
b/src/mem/ruby/slicc_interface/Controller.py
index ae4263c..4647678 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2017,2019 ARM Limited
+# Copyright (c) 2017,2019,2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -68,3 +68,8 @@
memory = MasterPort("Port for attaching a memory controller")
system = Param.System(Parent.any, "system object parameter")
+
+ # These can be used by a protocol to enable reuse of the same machine
+ # types to model different levels of the cache hierarchy
+ downstream_destinations = VectorParam.RubyController([],
+ "Possible destinations for requests sent towards
memory")
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/31415
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9a202e9461e0d2f16ed232ff8b60bbde2d15570d
Gerrit-Change-Number: 31415
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück <tiago.m...@arm.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
