Hello Tony Gutierrez,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/29944
to review the following change.
Change subject: arch-gcn3: Add support for rd/wr EXEC_HI to operand class
......................................................................
arch-gcn3: Add support for rd/wr EXEC_HI to operand class
Change-Id: Ib22dd604f88ea56801964235082835002deffca1
---
M src/arch/gcn3/operand.hh
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/src/arch/gcn3/operand.hh b/src/arch/gcn3/operand.hh
index 7f70fab..960d05e 100644
--- a/src/arch/gcn3/operand.hh
+++ b/src/arch/gcn3/operand.hh
@@ -435,13 +435,30 @@
if (!isScalarReg(_opIdx)) {
if (_opIdx == REG_EXEC_LO) {
- uint64_t new_exec_mask_val(0);
+ ScalarRegU64 new_exec_mask_val(0);
std::memcpy((void*)&new_exec_mask_val,
(void*)srfData.data(), sizeof(new_exec_mask_val));
VectorMask new_exec_mask(new_exec_mask_val);
wf->execMask() = new_exec_mask;
DPRINTF(GPUSRF, "Write EXEC\n");
DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val);
+ } else if (_opIdx == REG_EXEC_HI) {
+ /**
+ * If we're writing only the upper half of the EXEC
mask
+ * this ought to be a single dword operand.
+ */
+ assert(NumDwords == 1);
+ ScalarRegU32 new_exec_mask_hi_val(0);
+ ScalarRegU64 new_exec_mask_val
+ = wf->execMask().to_ullong();
+ std::memcpy((void*)&new_exec_mask_hi_val,
+ (void*)srfData.data(),
sizeof(new_exec_mask_hi_val));
+ replaceBits(new_exec_mask_val, 63, 32,
+ new_exec_mask_hi_val);
+ VectorMask new_exec_mask(new_exec_mask_val);
+ wf->execMask() = new_exec_mask;
+ DPRINTF(GPUSRF, "Write EXEC\n");
+ DPRINTF(GPUSRF, "EXEC = %#x\n", new_exec_mask_val);
} else {
_gpuDynInst->writeMiscReg(_opIdx, srfData[0]);
}
@@ -505,6 +522,23 @@
DPRINTF(GPUSRF, "EXEC = %#x\n", exec_mask);
}
break;
+ case REG_EXEC_HI:
+ {
+ /**
+ * If we're reading only the upper half of the EXEC
mask
+ * this ought to be a single dword operand.
+ */
+ assert(NumDwords == 1);
+ ScalarRegU64 exec_mask = _gpuDynInst->wavefront()
+ ->execMask().to_ullong();
+
+ ScalarRegU32 exec_mask_hi = bits(exec_mask, 63, 32);
+ std::memcpy((void*)srfData.data(),
(void*)&exec_mask_hi,
+ sizeof(srfData));
+ DPRINTF(GPUSRF, "Read EXEC_HI\n");
+ DPRINTF(GPUSRF, "EXEC_HI = %#x\n", exec_mask_hi);
+ }
+ break;
case REG_SRC_SWDA:
case REG_SRC_DPP:
case REG_SRC_LITERAL:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/29944
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib22dd604f88ea56801964235082835002deffca1
Gerrit-Change-Number: 29944
Gerrit-PatchSet: 1
Gerrit-Owner: Anthony Gutierrez <[email protected]>
Gerrit-Reviewer: Tony Gutierrez <[email protected]>
Gerrit-MessageType: newchange
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