Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/30324
to review the following change.
Change subject: cpu: Add HTM ThreadContext API
......................................................................
cpu: Add HTM ThreadContext API
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Change-Id: I9d60f69592c8072e70cef18787b5a4f2fc737a9d
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
6 files changed, 82 insertions(+), 8 deletions(-)
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index 52ea7d2..bb348cf 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -578,6 +578,17 @@
{
actualTC->setCCRegFlat(idx, val);
}
+
+ // hardware transactional memory
+ void htmAbortTransaction(uint64_t htmUid, HtmFailureFaultCause cause)
+ {
+ panic("function not implemented");
+ }
+
+ TheISA::HTMCheckpoint *getHTMCheckpointPtr()
+ {
+ panic("function not implemented");
+ }
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 3cb3e97..e9e3ff2 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -510,6 +510,10 @@
RegVal readCCRegFlat(RegIndex idx) const override;
void setCCRegFlat(RegIndex idx, RegVal val) override;
+
+ // hardware transactional memory
+ virtual void htmAbortTransaction(uint64_t, HtmFailureFaultCause);
+ virtual TheISA::HTMCheckpoint *getHTMCheckpointPtr();
};
#endif
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index d02be71..e458983 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, 2016-2017 ARM Limited
+ * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -359,4 +359,24 @@
conditionalSquash();
}
+// hardware transactional memory
+template <class Impl>
+void
+O3ThreadContext<Impl>::htmAbortTransaction(uint64_t htmUid,
+ HtmFailureFaultCause cause)
+{
+ cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);
+
+ conditionalSquash();
+}
+
+template <class Impl>
+TheISA::HTMCheckpoint*
+O3ThreadContext<Impl>::getHTMCheckpointPtr()
+{
+ conditionalSquash();
+
+ return &thread->htmCheckpoint;
+}
+
#endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index d0c6bf4..f685883 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -54,6 +54,7 @@
#include "cpu/base.hh"
#include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
+#include "cpu/simple/base.hh"
#include "cpu/thread_context.hh"
#include "mem/se_translating_port_proxy.hh"
#include "mem/translating_port_proxy.hh"
@@ -75,7 +76,8 @@
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
- system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
+ system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa)),
+ htmTransactionStarts(0), htmTransactionStops(0)
{
assert(isa);
clearArchRegs();
@@ -89,7 +91,8 @@
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
- system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa))
+ system(_sys), itb(_itb), dtb(_dtb), decoder(TheISA::Decoder(isa)),
+ htmTransactionStarts(0), htmTransactionStops(0)
{
assert(isa);
@@ -211,3 +214,23 @@
{
TheISA::copyRegs(src_tc, this);
}
+
+// hardware transactional memory
+void
+SimpleThread::htmAbortTransaction(uint64_t htmUid, HtmFailureFaultCause
cause)
+{
+ BaseSimpleCPU *baseSimpleCpu = dynamic_cast<BaseSimpleCPU*>(baseCpu);
+ assert(baseSimpleCpu);
+
+ baseSimpleCpu->htmSendAbortSignal(cause);
+
+ // these must be reset after the abort signal has been sent
+ htmTransactionStarts = 0;
+ htmTransactionStops = 0;
+}
+
+TheISA::HTMCheckpoint*
+SimpleThread::getHTMCheckpointPtr()
+{
+ return &_htmCheckpoint;
+}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 6118541..3c5871a 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -112,6 +112,9 @@
TheISA::PCState _pcState;
+ // hardware transactional memory
+ TheISA::HTMCheckpoint _htmCheckpoint;
+
/** Did this instruction execute or is it predicated false */
bool predicate;
@@ -138,6 +141,10 @@
TheISA::Decoder decoder;
+ // hardware transactional memory
+ int64_t htmTransactionStarts;
+ int64_t htmTransactionStops;
+
// constructor: initialize SimpleThread from given process structure
// FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
@@ -693,6 +700,10 @@
RegVal readCCRegFlat(RegIndex idx) const override { return
ccRegs[idx]; }
void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] =
val; }
+
+ // hardware transactional memory
+ void htmAbortTransaction(uint64_t, HtmFailureFaultCause);
+ TheISA::HTMCheckpoint *getHTMCheckpointPtr();
};
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 4907b84..0efbc45 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -46,6 +46,7 @@
#include <string>
#include "arch/generic/isa.hh"
+#include "arch/htm.hh"
#include "arch/registers.hh"
#include "arch/types.hh"
#include "base/types.hh"
@@ -353,6 +354,10 @@
virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
/** @} */
+ // hardware transactional memory
+ virtual void htmAbortTransaction(uint64_t htm_uid,
+ HtmFailureFaultCause cause) = 0;
+ virtual TheISA::HTMCheckpoint *getHTMCheckpointPtr() = 0;
};
/** @{ */
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30324
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d60f69592c8072e70cef18787b5a4f2fc737a9d
Gerrit-Change-Number: 30324
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Timothy Hayes <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
