Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/30324 )
Change subject: cpu: Add HTM ThreadContext API
......................................................................
cpu: Add HTM ThreadContext API
JIRA: https://gem5.atlassian.net/browse/GEM5-587
Change-Id: I9d60f69592c8072e70cef18787b5a4f2fc737a9d
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30324
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/cpu/checker/thread_context.hh
M src/cpu/o3/thread_context.hh
M src/cpu/o3/thread_context_impl.hh
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
6 files changed, 90 insertions(+), 6 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index e98b3a2..b5a974b 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -554,6 +554,26 @@
{
actualTC->setCCRegFlat(idx, val);
}
+
+ // hardware transactional memory
+ void
+ htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)
override
+ {
+ panic("function not implemented");
+ }
+
+ BaseHTMCheckpointPtr&
+ getHtmCheckpointPtr() override
+ {
+ panic("function not implemented");
+ }
+
+ void
+ setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override
+ {
+ panic("function not implemented");
+ }
+
};
#endif // __CPU_CHECKER_EXEC_CONTEXT_HH__
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e3e11fe..b3eba13 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -479,6 +479,12 @@
RegVal readCCRegFlat(RegIndex idx) const override;
void setCCRegFlat(RegIndex idx, RegVal val) override;
+
+ // hardware transactional memory
+ void htmAbortTransaction(uint64_t htm_uid,
+ HtmFailureFaultCause cause) override;
+ BaseHTMCheckpointPtr& getHtmCheckpointPtr() override;
+ void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
};
#endif
diff --git a/src/cpu/o3/thread_context_impl.hh
b/src/cpu/o3/thread_context_impl.hh
index a5db764..014b0f5 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, 2016-2017 ARM Limited
+ * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -325,4 +325,27 @@
conditionalSquash();
}
+// hardware transactional memory
+template <class Impl>
+void
+O3ThreadContext<Impl>::htmAbortTransaction(uint64_t htmUid,
+ HtmFailureFaultCause cause)
+{
+ panic("function not implemented\n");
+}
+
+template <class Impl>
+BaseHTMCheckpointPtr&
+O3ThreadContext<Impl>::getHtmCheckpointPtr()
+{
+ panic("function not implemented\n");
+}
+
+template <class Impl>
+void
+O3ThreadContext<Impl>::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
+{
+ panic("function not implemented\n");
+}
+
#endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 14551fb..b0ffc82 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 ARM Limited
+ * Copyright (c) 2018, 2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -50,6 +50,7 @@
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
+#include "cpu/simple/base.hh"
#include "cpu/thread_context.hh"
#include "mem/se_translating_port_proxy.hh"
#include "mem/translating_port_proxy.hh"
@@ -169,3 +170,22 @@
{
TheISA::copyRegs(src_tc, this);
}
+
+// hardware transactional memory
+void
+SimpleThread::htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause
cause)
+{
+ panic("function not implemented\n");
+}
+
+BaseHTMCheckpointPtr&
+SimpleThread::getHtmCheckpointPtr()
+{
+ panic("function not implemented\n");
+}
+
+void
+SimpleThread::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
+{
+ panic("function not implemented\n");
+}
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 2c78573..eb88104 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -45,6 +45,7 @@
#include <array>
#include "arch/decoder.hh"
+#include "arch/generic/htm.hh"
#include "arch/generic/tlb.hh"
#include "arch/isa.hh"
#include "arch/registers.hh"
@@ -58,6 +59,7 @@
#include "debug/IntRegs.hh"
#include "debug/VecPredRegs.hh"
#include "debug/VecRegs.hh"
+#include "mem/htm.hh"
#include "mem/page_table.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
@@ -661,6 +663,13 @@
RegVal readCCRegFlat(RegIndex idx) const override { return
ccRegs[idx]; }
void setCCRegFlat(RegIndex idx, RegVal val) override { ccRegs[idx] =
val; }
+
+ // hardware transactional memory
+ void htmAbortTransaction(uint64_t htm_uid,
+ HtmFailureFaultCause cause) override;
+
+ BaseHTMCheckpointPtr& getHtmCheckpointPtr() override;
+ void setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt) override;
};
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 6662502..c4fbaf4 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2012, 2016-2018 ARM Limited
+ * Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -45,6 +45,7 @@
#include <iostream>
#include <string>
+#include "arch/generic/htm.hh"
#include "arch/generic/isa.hh"
#include "arch/registers.hh"
#include "arch/types.hh"
@@ -340,6 +341,11 @@
virtual void setCCRegFlat(RegIndex idx, RegVal val) = 0;
/** @} */
+ // hardware transactional memory
+ virtual void htmAbortTransaction(uint64_t htm_uid,
+ HtmFailureFaultCause cause) = 0;
+ virtual BaseHTMCheckpointPtr& getHtmCheckpointPtr() = 0;
+ virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0;
};
/** @{ */
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9d60f69592c8072e70cef18787b5a4f2fc737a9d
Gerrit-Change-Number: 30324
Gerrit-PatchSet: 12
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Alexandru Duțu <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Timothy Hayes <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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