Giacomo Travaglini has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/30134 )

Change subject: sim: Add faulting flag to instruction tracing interface
......................................................................

sim: Add faulting flag to instruction tracing interface

This patch adds a faulting flag to InstRecord.
This allows tracers to identify that the traced instruction has
faulted, when ExecFaulting is enabled. It can be set with
InstRecord::setFaulting() and read with Instrecord::getFaulting().

Change-Id: I390392d59de930533eab101e96dc4d3c76500748
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30134
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/sim/insttracer.hh
1 file changed, 13 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 2e9806d..284e04a 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, 2017 ARM Limited
+ * Copyright (c) 2014, 2017, 2020 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -143,6 +143,12 @@
      */
     bool predicate;

+    /**
+     * Did the execution of this instruction fault? (requires ExecFaulting
+     * to be enabled)
+     */
+    bool faulting;
+
   public:
     InstRecord(Tick _when, ThreadContext *_thread,
                const StaticInstPtr _staticInst,
@@ -151,7 +157,8 @@
         : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
         macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
-        fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
+        fetch_seq_valid(false), cp_seq_valid(false), predicate(true),
+        faulting(false)
     { }

     virtual ~InstRecord()
@@ -218,6 +225,8 @@

     void setPredicate(bool val) { predicate = val; }

+    void setFaulting(bool val) { faulting = val; }
+
     virtual void dump() = 0;

   public:
@@ -241,6 +250,8 @@

     InstSeqNum getCpSeq() const { return cp_seq; }
     bool getCpSeqValid() const { return cp_seq_valid; }
+
+    bool getFaulting() const { return faulting; }
 };

 class InstTracer : public SimObject

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I390392d59de930533eab101e96dc4d3c76500748
Gerrit-Change-Number: 30134
Gerrit-PatchSet: 4
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Anthony Gutierrez <anthony.gutier...@amd.com>
Gerrit-Reviewer: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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