Call for review: Arm’s Transactional Memory Extension (TME)

We have recently uploaded a set of large patches that introduce
  (a)Partial support for hardware transactional memory (HTM) in gem5
  (b)Architectural support in the Arm ISA for the Transactional Memory 
Extension (TME)

HTM support is implemented in the Ruby memory system—specifically by modifying 
the MESI_Three_Level protocol. Various additions are made to the APIs of CPU, 
ExecContext and ThreadContext. The existing fault/exception system is reused to 
handle transactional aborts and architectural checkpoint restorations. Both 
TimingSimpleCPU and O3CPU are augmented to support general HTM functionality. 
HTM support is a reworking of a previous pull request from Pradip Vallathol 
from his master’s thesis done at The University of Wisconsin-Madison.

Arm’s TME ISA adds four new instructions:
  - TSTART – Creates an architectural checkpoint and places the CPU and cache 
hierarchy into transactional state in which all subsequent operations are 
executed speculatively and are not visible to the rest of the system until 
committed atomically.
  - TCOMMIT – Makes all speculative (transactional) operations globally visible 
and removes the CPU and cache hierarchy from transactional state.
  - TCANCEL – Discards all speculative memory operations, rolls back the 
architectural state to a checkpoint taken at TSTART and removes the CPU and 
cache hierarchy from transactional state.
  - TTEST – Returns the current transactional depth (e.g. if TSTART is called 
inside a transaction), or a zero if not in transactional state.

Gerrit patchset:

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