Tiago Mück has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31418 )
Change subject: configs,tests: use Sequencer port connect methods
......................................................................
configs,tests: use Sequencer port connect methods
This patch updates Ruby configuration scripts to use the functions
defined in the RubySequencer python object to connect to cpu ports.
Only the protocol-agnostic scripts were updated. Scripts that assume
a specific protocol (e.g. configs/example/apu_se.py, gpu tests, etc)
were not changed as they require a specific port wireup.
Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Signed-off-by: Tiago Mück <[email protected]>
---
M configs/example/fs.py
M configs/example/garnet_synth_traffic.py
M configs/example/ruby_direct_test.py
M configs/example/ruby_mem_test.py
M configs/example/ruby_random_test.py
M configs/example/se.py
M tests/configs/memtest-ruby.py
M tests/configs/pc-simple-timing-ruby.py
M tests/configs/rubytest-ruby.py
9 files changed, 13 insertions(+), 37 deletions(-)
diff --git a/configs/example/fs.py b/configs/example/fs.py
index d39feee..1cd53db 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -172,17 +172,7 @@
cpu.createThreads()
cpu.createInterruptController()
- cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
- cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
-
- if buildEnv['TARGET_ISA'] in ("x86", "arm"):
- cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
- cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
-
- if buildEnv['TARGET_ISA'] in "x86":
- cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
- cpu.interrupts[0].int_master =
test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts[0].int_slave =
test_sys.ruby._cpu_ports[i].master
+ test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu)
else:
if options.caches or options.l2cache:
diff --git a/configs/example/garnet_synth_traffic.py
b/configs/example/garnet_synth_traffic.py
index 9878c23..ebc43da 100644
--- a/configs/example/garnet_synth_traffic.py
+++ b/configs/example/garnet_synth_traffic.py
@@ -134,7 +134,7 @@
#
# Tie the cpu test ports to the ruby cpu port
#
- cpus[i].test = ruby_port.slave
+ ruby_port.connectDataPort(cpus[i], 'test')
i += 1
# -----------------------
diff --git a/configs/example/ruby_direct_test.py
b/configs/example/ruby_direct_test.py
index 89a2351..9d3bb02 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -112,7 +112,7 @@
#
# Tie the ruby tester ports to the ruby cpu ports
#
- system.cpu.cpuPort = ruby_port.slave
+ ruby_port.connectDataPort(system.cpu, 'cpuPort')
# -----------------------
# run simulation
diff --git a/configs/example/ruby_mem_test.py
b/configs/example/ruby_mem_test.py
index 310ee3c..316cf10 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -140,7 +140,7 @@
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.port = system.ruby._cpu_ports[i].slave
+ system.ruby._cpu_ports[i].connectDataPort(cpu, 'port')
#
# Since the memtester is incredibly bursty, increase the deadlock
diff --git a/configs/example/ruby_random_test.py
b/configs/example/ruby_random_test.py
index 68402d5..75ab86f 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -127,11 +127,11 @@
# Tie the ruby tester ports to the ruby cpu read and write ports
#
if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
- tester.cpuInstDataPort = ruby_port.slave
+ ruby_port.connectDataPort(tester, 'cpuInstDataPort')
elif ruby_port.support_data_reqs:
- tester.cpuDataPort = ruby_port.slave
+ ruby_port.connectDataPort(tester, 'cpuDataPort')
elif ruby_port.support_inst_reqs:
- tester.cpuInstPort = ruby_port.slave
+ ruby_port.connectInstPort(tester, 'cpuInstPort')
# Do not automatically retry stalled Ruby requests
ruby_port.no_retry_on_stall = True
diff --git a/configs/example/se.py b/configs/example/se.py
index 200a0de..1146ea9 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -259,14 +259,7 @@
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
- system.cpu[i].icache_port = ruby_port.slave
- system.cpu[i].dcache_port = ruby_port.slave
- if buildEnv['TARGET_ISA'] == 'x86':
- system.cpu[i].interrupts[0].pio = ruby_port.master
- system.cpu[i].interrupts[0].int_master = ruby_port.slave
- system.cpu[i].interrupts[0].int_slave = ruby_port.master
- system.cpu[i].itb.walker.port = ruby_port.slave
- system.cpu[i].dtb.walker.port = ruby_port.slave
+ ruby_port.connectCpuPorts(system.cpu[i])
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 7aca77f..12d3ce3 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -100,7 +100,7 @@
# Tie the cpu port to the ruby cpu ports and
# physmem, respectively
#
- cpus[i].port = ruby_port.slave
+ ruby_port.connectDataPort(cpus[i], 'port')
#
# Since the memtester is incredibly bursty, increase the deadlock
diff --git a/tests/configs/pc-simple-timing-ruby.py
b/tests/configs/pc-simple-timing-ruby.py
index 06a3efc..884fd7d 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -78,14 +78,7 @@
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
- cpu.icache_port = system.ruby._cpu_ports[i].slave
- cpu.dcache_port = system.ruby._cpu_ports[i].slave
- cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
- cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
-
- cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
- cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
- cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
+ system.ruby._cpu_ports[i].connectCpuPorts(cpu)
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index 5c01cff..cf7c43b 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -101,11 +101,11 @@
# Tie the ruby tester ports to the ruby cpu read and write ports
#
if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
- tester.cpuInstDataPort = ruby_port.slave
+ ruby_port.connectDataPort(tester, 'cpuInstDataPort')
elif ruby_port.support_data_reqs:
- tester.cpuDataPort = ruby_port.slave
+ ruby_port.connectDataPort(tester, 'cpuDataPort')
elif ruby_port.support_inst_reqs:
- tester.cpuInstPort = ruby_port.slave
+ ruby_port.connectInstPort(tester, 'cpuInstPort')
# Do not automatically retry stalled Ruby requests
ruby_port.no_retry_on_stall = True
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Gerrit-Change-Number: 31418
Gerrit-PatchSet: 1
Gerrit-Owner: Tiago Mück <[email protected]>
Gerrit-MessageType: newchange
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