Tiago Mück has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/31418 )
Change subject: configs,tests: use Sequencer port connect methods
......................................................................
configs,tests: use Sequencer port connect methods
This patch updates Ruby configuration scripts to use the functions
defined in the RubySequencer python object to connect to cpu ports.
Only the protocol-agnostic scripts were updated. Scripts that assume
a specific protocol (e.g. configs/example/apu_se.py, gpu tests, etc)
and scripts in which the obj connected to the RubySequencer is not a
BaseCPU (e.g. the tests scripts) were not changed as they require a
non-standard port wireup.
Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Signed-off-by: Tiago Mück <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31418
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M configs/example/fs.py
M configs/example/se.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M configs/ruby/Ruby.py
M tests/configs/pc-simple-timing-ruby.py
6 files changed, 6 insertions(+), 50 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 229c50e..1cd53db 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -172,17 +172,7 @@
cpu.createThreads()
cpu.createInterruptController()
- cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
- cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
-
- cpu.mmu.connectWalkerPorts(
- test_sys.ruby._cpu_ports[i].slave,
- test_sys.ruby._cpu_ports[i].slave)
-
- if buildEnv['TARGET_ISA'] in "x86":
- cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
- cpu.interrupts[0].int_master =
test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts[0].int_slave =
test_sys.ruby._cpu_ports[i].master
+ test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu)
else:
if options.caches or options.l2cache:
diff --git a/configs/example/se.py b/configs/example/se.py
index f29008e..9119c40 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -260,14 +260,7 @@
system.cpu[i].createInterruptController()
# Connect the cpu's cache ports to Ruby
- system.cpu[i].icache_port = ruby_port.slave
- system.cpu[i].dcache_port = ruby_port.slave
- if buildEnv['TARGET_ISA'] == 'x86':
- system.cpu[i].interrupts[0].pio = ruby_port.master
- system.cpu[i].interrupts[0].int_master = ruby_port.slave
- system.cpu[i].interrupts[0].int_slave = ruby_port.master
- system.cpu[i].mmu.connectWalkerPorts(
- ruby_port.slave, ruby_port.slave)
+ ruby_port.connectCpuPorts(system.cpu[i])
else:
MemClass = Simulation.setMemClass(options)
system.membus = SystemXBar()
diff --git a/configs/learning_gem5/part3/msi_caches.py
b/configs/learning_gem5/part3/msi_caches.py
index 86adfd5..822d98a 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -105,15 +105,7 @@
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].slave, self.sequencers[i].slave)
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py
b/configs/learning_gem5/part3/ruby_caches_MI_example.py
index ac003ff..e7d20dd 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -103,15 +103,7 @@
# Connect the cpu's cache, interrupt, and TLB ports to Ruby
for i,cpu in enumerate(cpus):
- cpu.icache_port = self.sequencers[i].slave
- cpu.dcache_port = self.sequencers[i].slave
- cpu.mmu.connectWalkerPorts(
- self.sequencers[i].slave, self.sequencers[i].slave)
- isa = buildEnv['TARGET_ISA']
- if isa == 'x86':
- cpu.interrupts[0].pio = self.sequencers[i].master
- cpu.interrupts[0].int_master = self.sequencers[i].slave
- cpu.interrupts[0].int_slave = self.sequencers[i].master
+ self.sequencers[i].connectCpuPorts(cpu)
class L1Cache(L1Cache_Controller):
diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index 86d5748..8aa99be 100644
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -226,11 +226,7 @@
# Connect the cpu sequencers and the piobus
if piobus != None:
for cpu_seq in cpu_sequencers:
- cpu_seq.pio_master_port = piobus.slave
- cpu_seq.mem_master_port = piobus.slave
-
- if buildEnv['TARGET_ISA'] == "x86":
- cpu_seq.pio_slave_port = piobus.master
+ cpu_seq.connectIOPorts(piobus)
ruby.number_of_virtual_networks =
ruby.network.number_of_virtual_networks
ruby._cpu_ports = cpu_sequencers
diff --git a/tests/configs/pc-simple-timing-ruby.py
b/tests/configs/pc-simple-timing-ruby.py
index c78033b..884fd7d 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -78,14 +78,7 @@
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
- cpu.icache_port = system.ruby._cpu_ports[i].slave
- cpu.dcache_port = system.ruby._cpu_ports[i].slave
- cpu.mmu.connectWalkerPorts(
- system.ruby._cpu_ports[i].slave, system.ruby._cpu_ports[i].slave)
-
- cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
- cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
- cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
+ system.ruby._cpu_ports[i].connectCpuPorts(cpu)
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1e931ff0fc93f393cb36fbb8769ea4b48e1a1e86
Gerrit-Change-Number: 31418
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Mück <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Tiago Mück <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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