Ian Jiang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/32694 )
Change subject: arch-riscv: Fix disassembling of all register instructions
......................................................................
arch-riscv: Fix disassembling of all register instructions
How many Rs to output in disassembling register instructions? It does
not depend on wheather the register index is zero, but on the count
of source registers.
This patch fixes the problem.
Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Signed-off-by: Ian Jiang <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32694
Reviewed-by: Jason Lowe-Power <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/insts/standard.cc
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/insts/standard.cc
b/src/arch/riscv/insts/standard.cc
index e6c2b67..9a9aa9d 100644
--- a/src/arch/riscv/insts/standard.cc
+++ b/src/arch/riscv/insts/standard.cc
@@ -48,9 +48,9 @@
stringstream ss;
ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
registerName(_srcRegIdx[0]);
- if (_srcRegIdx[1].index() != 0)
+ if (_numSrcRegs >= 2)
ss << ", " << registerName(_srcRegIdx[1]);
- if (_srcRegIdx[2].index() != 0)
+ if (_numSrcRegs >= 3)
ss << ", " << registerName(_srcRegIdx[2]);
return ss.str();
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9a770722003bc6f4a259589a7471a506494d4c86
Gerrit-Change-Number: 32694
Gerrit-PatchSet: 2
Gerrit-Owner: Ian Jiang <[email protected]>
Gerrit-Reviewer: Alec Roelke <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Ian Jiang <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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