Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33547 )
Change subject: gpu-compute: update print statements + master/slave
variables
......................................................................
gpu-compute: update print statements + master/slave variables
Change-Id: I6fb925294d5fd2c670d15c0d895a43ef6c371ae3
---
M src/gpu-compute/X86GPUTLB.py
M src/gpu-compute/gpu_tlb.cc
M src/gpu-compute/tlb_coalescer.cc
M src/gpu-compute/tlb_coalescer.hh
4 files changed, 24 insertions(+), 20 deletions(-)
diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py
index bd22bee..ab48a52 100644
--- a/src/gpu-compute/X86GPUTLB.py
+++ b/src/gpu-compute/X86GPUTLB.py
@@ -58,8 +58,10 @@
missLatency1 = Param.Int(5, "Latency #1 of a TLB miss")
missLatency2 = Param.Int(100, "Latency #2 of a TLB miss")
maxOutstandingReqs = Param.Int(64, "# of maximum outstanding requests")
- slave = VectorSlavePort("Port on side closer to CPU/CU")
- master = VectorMasterPort("Port on side closer to memory")
+ cpu_side = VectorSlavePort("Port on side closer to CPU/CU")
+ slave = DeprecatedParam(cpu_side, '`slave` is now called
`cpu_side`')
+ mem_side = VectorMasterPort("Port on side closer to memory")
+ master = DeprecatedParam(mem_side, '`master` is now called
`mem_side`')
allocationPolicy = Param.Bool(True, "Allocate on an access")
accessDistance = Param.Bool(False, "print accessDistance stats")
@@ -69,6 +71,8 @@
cxx_header = 'gpu-compute/tlb_coalescer.hh'
probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
coalescingWindow = Param.Int(1, "Permit coalescing across that many
ticks")
- slave = VectorSlavePort("Port on side closer to CPU/CU")
- master = VectorMasterPort("Port on side closer to memory")
+ cpu_side = VectorSlavePort("Port on side closer to CPU/CU")
+ slave = DeprecatedParam(cpu_side, '`slave` is now called
`cpu_side`')
+ mem_side = VectorMasterPort("Port on side closer to memory")
+ master DeprecatedParam(mem_side, '`master` is now called `mem_side`')
disableCoalescing = Param.Bool(False,"Dispable Coalescing")
diff --git a/src/gpu-compute/gpu_tlb.cc b/src/gpu-compute/gpu_tlb.cc
index a37618d..4e67ecd 100644
--- a/src/gpu-compute/gpu_tlb.cc
+++ b/src/gpu-compute/gpu_tlb.cc
@@ -112,14 +112,14 @@
missLatency1 = p->missLatency1;
missLatency2 = p->missLatency2;
- // create the slave ports based on the number of connected ports
- for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
+ // create the response ports based on the number of connected ports
+ for (size_t i = 0; i < p->port_cpu_side_connection_count; ++i) {
cpuSidePort.push_back(new CpuSidePort(csprintf("%s-port%d",
name(), i), this, i));
}
- // create the master ports based on the number of connected ports
- for (size_t i = 0; i < p->port_master_connection_count; ++i) {
+ // create the request ports based on the number of connected ports
+ for (size_t i = 0; i < p->port_mem_side_connection_count; ++i) {
memSidePort.push_back(new MemSidePort(csprintf("%s-port%d",
name(), i), this, i));
}
@@ -135,13 +135,13 @@
Port &
GpuTLB::getPort(const std::string &if_name, PortID idx)
{
- if (if_name == "slave") {
+ if (if_name == "cpu_side") {
if (idx >= static_cast<PortID>(cpuSidePort.size())) {
panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *cpuSidePort[idx];
- } else if (if_name == "master") {
+ } else if (if_name == "mem_side") {
if (idx >= static_cast<PortID>(memSidePort.size())) {
panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
@@ -1323,7 +1323,7 @@
AddrRangeList
GpuTLB::CpuSidePort::getAddrRanges() const
{
- // currently not checked by the master
+ // currently not checked by the requestor
AddrRangeList ranges;
return ranges;
diff --git a/src/gpu-compute/tlb_coalescer.cc
b/src/gpu-compute/tlb_coalescer.cc
index b591232..eccd328 100644
--- a/src/gpu-compute/tlb_coalescer.cc
+++ b/src/gpu-compute/tlb_coalescer.cc
@@ -51,14 +51,14 @@
"Cleanup issuedTranslationsTable hashmap",
false, Event::Maximum_Pri)
{
- // create the slave ports based on the number of connected ports
- for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
+ // create the response ports based on the number of connected ports
+ for (size_t i = 0; i < p->port_cpu_side_connection_count; ++i) {
cpuSidePort.push_back(new CpuSidePort(csprintf("%s-port%d",
name(), i),
this, i));
}
- // create the master ports based on the number of connected ports
- for (size_t i = 0; i < p->port_master_connection_count; ++i) {
+ // create the request ports based on the number of connected ports
+ for (size_t i = 0; i < p->port_mem_side_connection_count; ++i) {
memSidePort.push_back(new MemSidePort(csprintf("%s-port%d",
name(), i),
this, i));
}
@@ -67,13 +67,13 @@
Port &
TLBCoalescer::getPort(const std::string &if_name, PortID idx)
{
- if (if_name == "slave") {
+ if (if_name == "cpu_side") {
if (idx >= static_cast<PortID>(cpuSidePort.size())) {
panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
return *cpuSidePort[idx];
- } else if (if_name == "master") {
+ } else if (if_name == "mem_side") {
if (idx >= static_cast<PortID>(memSidePort.size())) {
panic("TLBCoalescer::getPort: unknown index %d\n", idx);
}
@@ -358,7 +358,7 @@
AddrRangeList
TLBCoalescer::CpuSidePort::getAddrRanges() const
{
- // currently not checked by the master
+ // currently not checked by the requestor
AddrRangeList ranges;
return ranges;
diff --git a/src/gpu-compute/tlb_coalescer.hh
b/src/gpu-compute/tlb_coalescer.hh
index aff2515..7c42362 100644
--- a/src/gpu-compute/tlb_coalescer.hh
+++ b/src/gpu-compute/tlb_coalescer.hh
@@ -192,9 +192,9 @@
}
};
- // Coalescer slave ports on the cpu Side
+ // Coalescer response ports on the cpu Side
std::vector<CpuSidePort*> cpuSidePort;
- // Coalescer master ports on the memory side
+ // Coalescer request ports on the memory side
std::vector<MemSidePort*> memSidePort;
Port &getPort(const std::string &if_name,
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/33547
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6fb925294d5fd2c670d15c0d895a43ef6c371ae3
Gerrit-Change-Number: 33547
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <[email protected]>
Gerrit-MessageType: newchange
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