Shivani Parekh has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/33541 )
Change subject: mem-cache: Update variables master/slave
......................................................................
mem-cache: Update variables master/slave
Change-Id: I42942bd0880c8892b536d44865c1dd807f2aa030
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
M src/mem/cache/cache_blk.cc
M src/mem/cache/cache_blk.hh
M src/mem/cache/prefetch/Prefetcher.py
M src/mem/cache/prefetch/stride.cc
M src/mem/cache/prefetch/stride.hh
M src/mem/cache/tags/base.cc
M src/mem/cache/tags/base.hh
M src/mem/cache/tags/sector_blk.cc
M src/mem/cache/tags/sector_blk.hh
11 files changed, 78 insertions(+), 77 deletions(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index f92f87b..ab2d02b 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -114,7 +114,7 @@
// buffer before committing to an MSHR
// forward snoops is overridden in init() once we can query
- // whether the connected master is actually snooping or not
+ // whether the connected requestor is actually snooping or not
tempBlock = new TempCacheBlk(blkSize);
@@ -1868,98 +1868,98 @@
Stats::Group::regStats();
System *system = cache.system;
- const auto max_masters = system->maxMasters();
+ const auto max_requestors = system->maxMasters();
hits
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
hits.subname(i, system->getMasterName(i));
}
// Miss statistics
misses
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
misses.subname(i, system->getMasterName(i));
}
// Miss latency statistics
missLatency
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
missLatency.subname(i, system->getMasterName(i));
}
// access formulas
accesses.flags(total | nozero | nonan);
accesses = hits + misses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
accesses.subname(i, system->getMasterName(i));
}
// miss rate formulas
missRate.flags(total | nozero | nonan);
missRate = misses / accesses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
missRate.subname(i, system->getMasterName(i));
}
// miss latency formulas
avgMissLatency.flags(total | nozero | nonan);
avgMissLatency = missLatency / misses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
avgMissLatency.subname(i, system->getMasterName(i));
}
// MSHR statistics
// MSHR hit statistics
mshr_hits
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
mshr_hits.subname(i, system->getMasterName(i));
}
// MSHR miss statistics
mshr_misses
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
mshr_misses.subname(i, system->getMasterName(i));
}
// MSHR miss latency statistics
mshr_miss_latency
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
mshr_miss_latency.subname(i, system->getMasterName(i));
}
// MSHR uncacheable statistics
mshr_uncacheable
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
mshr_uncacheable.subname(i, system->getMasterName(i));
}
// MSHR miss latency statistics
mshr_uncacheable_lat
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
mshr_uncacheable_lat.subname(i, system->getMasterName(i));
}
@@ -1967,21 +1967,21 @@
mshrMissRate.flags(total | nozero | nonan);
mshrMissRate = mshr_misses / accesses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
mshrMissRate.subname(i, system->getMasterName(i));
}
// mshrMiss latency formulas
avgMshrMissLatency.flags(total | nozero | nonan);
avgMshrMissLatency = mshr_miss_latency / mshr_misses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
avgMshrMissLatency.subname(i, system->getMasterName(i));
}
// mshrUncacheable latency formulas
avgMshrUncacheableLatency.flags(total | nozero | nonan);
avgMshrUncacheableLatency = mshr_uncacheable_lat / mshr_uncacheable;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
avgMshrUncacheableLatency.subname(i, system->getMasterName(i));
}
}
@@ -2063,7 +2063,7 @@
Stats::Group::regStats();
System *system = cache.system;
- const auto max_masters = system->maxMasters();
+ const auto max_requestors = system->maxMasters();
for (auto &cs : cmd)
cs->regStatsFromParent();
@@ -2083,73 +2083,73 @@
demandHits.flags(total | nozero | nonan);
demandHits = SUM_DEMAND(hits);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandHits.subname(i, system->getMasterName(i));
}
overallHits.flags(total | nozero | nonan);
overallHits = demandHits + SUM_NON_DEMAND(hits);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallHits.subname(i, system->getMasterName(i));
}
demandMisses.flags(total | nozero | nonan);
demandMisses = SUM_DEMAND(misses);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandMisses.subname(i, system->getMasterName(i));
}
overallMisses.flags(total | nozero | nonan);
overallMisses = demandMisses + SUM_NON_DEMAND(misses);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMisses.subname(i, system->getMasterName(i));
}
demandMissLatency.flags(total | nozero | nonan);
demandMissLatency = SUM_DEMAND(missLatency);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandMissLatency.subname(i, system->getMasterName(i));
}
overallMissLatency.flags(total | nozero | nonan);
overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMissLatency.subname(i, system->getMasterName(i));
}
demandAccesses.flags(total | nozero | nonan);
demandAccesses = demandHits + demandMisses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandAccesses.subname(i, system->getMasterName(i));
}
overallAccesses.flags(total | nozero | nonan);
overallAccesses = overallHits + overallMisses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallAccesses.subname(i, system->getMasterName(i));
}
demandMissRate.flags(total | nozero | nonan);
demandMissRate = demandMisses / demandAccesses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandMissRate.subname(i, system->getMasterName(i));
}
overallMissRate.flags(total | nozero | nonan);
overallMissRate = overallMisses / overallAccesses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMissRate.subname(i, system->getMasterName(i));
}
demandAvgMissLatency.flags(total | nozero | nonan);
demandAvgMissLatency = demandMissLatency / demandMisses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandAvgMissLatency.subname(i, system->getMasterName(i));
}
overallAvgMissLatency.flags(total | nozero | nonan);
overallAvgMissLatency = overallMissLatency / overallMisses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallAvgMissLatency.subname(i, system->getMasterName(i));
}
@@ -2175,54 +2175,54 @@
unusedPrefetches.flags(nozero);
writebacks
- .init(max_masters)
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
writebacks.subname(i, system->getMasterName(i));
}
demandMshrHits.flags(total | nozero | nonan);
demandMshrHits = SUM_DEMAND(mshr_hits);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandMshrHits.subname(i, system->getMasterName(i));
}
overallMshrHits.flags(total | nozero | nonan);
overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMshrHits.subname(i, system->getMasterName(i));
}
demandMshrMisses.flags(total | nozero | nonan);
demandMshrMisses = SUM_DEMAND(mshr_misses);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandMshrMisses.subname(i, system->getMasterName(i));
}
overallMshrMisses.flags(total | nozero | nonan);
overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMshrMisses.subname(i, system->getMasterName(i));
}
demandMshrMissLatency.flags(total | nozero | nonan);
demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandMshrMissLatency.subname(i, system->getMasterName(i));
}
overallMshrMissLatency.flags(total | nozero | nonan);
overallMshrMissLatency =
demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMshrMissLatency.subname(i, system->getMasterName(i));
}
overallMshrUncacheable.flags(total | nozero | nonan);
overallMshrUncacheable =
SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMshrUncacheable.subname(i, system->getMasterName(i));
}
@@ -2231,38 +2231,38 @@
overallMshrUncacheableLatency =
SUM_DEMAND(mshr_uncacheable_lat) +
SUM_NON_DEMAND(mshr_uncacheable_lat);
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
}
demandMshrMissRate.flags(total | nozero | nonan);
demandMshrMissRate = demandMshrMisses / demandAccesses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandMshrMissRate.subname(i, system->getMasterName(i));
}
overallMshrMissRate.flags(total | nozero | nonan);
overallMshrMissRate = overallMshrMisses / overallAccesses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallMshrMissRate.subname(i, system->getMasterName(i));
}
demandAvgMshrMissLatency.flags(total | nozero | nonan);
demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
}
overallAvgMshrMissLatency.flags(total | nozero | nonan);
overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
}
overallAvgMshrUncacheableLatency.flags(total | nozero | nonan);
overallAvgMshrUncacheableLatency =
overallMshrUncacheableLatency / overallMshrUncacheable;
- for (int i = 0; i < max_masters; i++) {
+ for (int i = 0; i < max_requestors; i++) {
overallAvgMshrUncacheableLatency.subname(i,
system->getMasterName(i));
}
@@ -2290,7 +2290,7 @@
assert(pkt->isResponse());
- // Express snoop responses from master to slave, e.g., from L1 to L2
+ // Express snoop responses from requestor to responder, e.g., from L1
to L2
cache->recvTimingSnoopResp(pkt);
return true;
}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index c129661..b10affa 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -111,7 +111,7 @@
protected:
/**
- * A cache master port is used for the memory-side port of the
+ * A cache request port is used for the memory-side port of the
* cache, and in addition to the basic timing port that only sends
* response packets through a transmit list, it also offers the
* ability to schedule and send request packets (requests &
@@ -202,7 +202,7 @@
/**
- * The memory-side port extends the base cache master port with
+ * The memory-side port extends the base cache request port with
* access functions for functional, atomic and timing snoops.
*/
class MemSidePort : public CacheMasterPort
@@ -234,9 +234,9 @@
};
/**
- * A cache slave port is used for the CPU-side port of the cache,
+ * A cache response port is used for the CPU-side port of the cache,
* and it is basically a simple timing port that uses a transmit
- * list for responses to the CPU (or connected master). In
+ * list for responses to the CPU (or connected requestor). In
* addition, it has the functionality to block the port for
* incoming requests. If blocked, the port will issue a retry once
* unblocked.
@@ -275,7 +275,7 @@
};
/**
- * The CPU-side port extends the base cache slave port with access
+ * The CPU-side port extends the base cache response port with access
* functions for functional, atomic and timing requests.
*/
class CpuSidePort : public CacheSlavePort
@@ -1154,7 +1154,7 @@
/**
* Marks the access path of the cache as blocked for the given cause.
This
- * also sets the blocked flag in the slave interface.
+ * also sets the blocked flag in the response interface.
* @param cause The reason for the cache blocking.
*/
void setBlocked(BlockedCause cause)
diff --git a/src/mem/cache/cache_blk.cc b/src/mem/cache/cache_blk.cc
index c4730ca..b31cb4f 100644
--- a/src/mem/cache/cache_blk.cc
+++ b/src/mem/cache/cache_blk.cc
@@ -44,7 +44,7 @@
void
CacheBlk::insert(const Addr tag, const bool is_secure,
- const int src_master_ID, const uint32_t task_ID)
+ const int src_requestor_ID, const uint32_t task_ID)
{
// Make sure that the block has been properly invalidated
assert(status == 0);
@@ -53,7 +53,7 @@
this->tag = tag;
// Set source requestor ID
- srcMasterId = src_master_ID;
+ srcUniqueId = src_requestor_ID;
// Set task ID
task_id = task_ID;
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index 3b94cf7..401c980 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -114,7 +114,7 @@
unsigned refCount;
/** holds the source requestor ID for this block. */
- int srcMasterId;
+ int srcUniqueId;
/**
* Tick on which the block was inserted in the cache. Its value is only
@@ -215,7 +215,7 @@
status = 0;
whenReady = MaxTick;
refCount = 0;
- srcMasterId = Request::invldUniqueId;
+ srcUniqueId = Request::invldUniqueId;
lockList.clear();
}
@@ -296,11 +296,11 @@
*
* @param tag Block address tag.
* @param is_secure Whether the block is in secure space or not.
- * @param src_master_ID The source requestor ID.
+ * @param src_requestor_ID The source requestor ID.
* @param task_ID The new task ID.
*/
virtual void insert(const Addr tag, const bool is_secure,
- const int src_master_ID, const uint32_t task_ID);
+ const int src_requestor_ID, const uint32_t
task_ID);
/**
* Track the fact that a local locked was issued to the
@@ -469,7 +469,8 @@
}
void insert(const Addr addr, const bool is_secure,
- const int src_master_ID=0, const uint32_t task_ID=0)
override
+ const int src_requestor_ID=0, const uint32_t task_ID=0)
+ override
{
// Make sure that the block has been properly invalidated
assert(status == 0);
diff --git a/src/mem/cache/prefetch/Prefetcher.py
b/src/mem/cache/prefetch/Prefetcher.py
index c163028..758803f 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -163,7 +163,7 @@
confidence_threshold = Param.Percent(50,
"Prefetch generation confidence threshold")
- use_master_id = Param.Bool(True, "Use master id based history")
+ use_requestor_id = Param.Bool(True, "Use requestor id based history")
degree = Param.Int(4, "Number of prefetches to generate")
diff --git a/src/mem/cache/prefetch/stride.cc
b/src/mem/cache/prefetch/stride.cc
index e6544db..3775eb8 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -77,7 +77,7 @@
: Queued(p),
initConfidence(p->confidence_counter_bits, p->initial_confidence),
threshConf(p->confidence_threshold/100.0),
- useMasterId(p->use_master_id),
+ useUniqueId(p->use_requestor_id),
degree(p->degree),
pcTableInfo(p->table_assoc, p->table_entries, p->table_indexing_policy,
p->table_replacement_policy)
@@ -124,7 +124,7 @@
Addr pf_addr = pfi.getAddr();
Addr pc = pfi.getPC();
bool is_secure = pfi.isSecure();
- MasterID unique_id = useMasterId ? pfi.getMasterId() : 0;
+ MasterID unique_id = useUniqueId ? pfi.getMasterId() : 0;
// Get corresponding pc table
PCTable* pcTable = findTable(unique_id);
diff --git a/src/mem/cache/prefetch/stride.hh
b/src/mem/cache/prefetch/stride.hh
index 72e335b..c64d263 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -94,7 +94,7 @@
/** Confidence threshold for prefetch generation. */
const double threshConf;
- const bool useMasterId;
+ const bool useUniqueId;
const int degree;
diff --git a/src/mem/cache/tags/base.cc b/src/mem/cache/tags/base.cc
index df29a85..070a6bf 100644
--- a/src/mem/cache/tags/base.cc
+++ b/src/mem/cache/tags/base.cc
@@ -109,7 +109,7 @@
assert(unique_id < system->maxMasters());
stats.occupancies[unique_id]++;
- // Insert block with tag, src master id and task id
+ // Insert block with tag, src unique id and task id
blk->insert(extractTag(pkt->getAddr()), pkt->isSecure(), unique_id,
pkt->req->taskId());
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index 5f02462..f8828ec 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -253,7 +253,7 @@
assert(blk);
assert(blk->isValid());
- stats.occupancies[blk->srcMasterId]--;
+ stats.occupancies[blk->srcUniqueId]--;
stats.totalRefs += blk->refCount;
stats.sampledRefs++;
diff --git a/src/mem/cache/tags/sector_blk.cc
b/src/mem/cache/tags/sector_blk.cc
index cea3d65..e914cef 100644
--- a/src/mem/cache/tags/sector_blk.cc
+++ b/src/mem/cache/tags/sector_blk.cc
@@ -92,7 +92,7 @@
void
SectorSubBlk::insert(const Addr tag, const bool is_secure,
- const int src_master_ID, const uint32_t task_ID)
+ const int src_requestor_ID, const uint32_t task_ID)
{
// Make sure it is not overwriting another sector
panic_if((_sectorBlk && _sectorBlk->isValid()) &&
@@ -100,7 +100,7 @@
(_sectorBlk->isSecure() != is_secure)),
"Overwriting valid sector!");
- CacheBlk::insert(tag, is_secure, src_master_ID, task_ID);
+ CacheBlk::insert(tag, is_secure, src_requestor_ID, task_ID);
// Set sector tag
_sectorBlk->setTag(tag);
diff --git a/src/mem/cache/tags/sector_blk.hh
b/src/mem/cache/tags/sector_blk.hh
index 0a9087e..5538aa1 100644
--- a/src/mem/cache/tags/sector_blk.hh
+++ b/src/mem/cache/tags/sector_blk.hh
@@ -122,11 +122,11 @@
*
* @param tag Block address tag.
* @param is_secure Whether the block is in secure space or not.
- * @param src_master_ID The source requestor ID.
+ * @param src_requestor_ID The source requestor ID.
* @param task_ID The new task ID.
*/
- void insert(const Addr tag, const bool is_secure, const int
src_master_ID,
- const uint32_t task_ID) override;
+ void insert(const Addr tag, const bool is_secure, const int
+ src_requestor_ID, const uint32_t task_ID) override;
/**
* Pretty-print sector offset and other CacheBlk information.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42942bd0880c8892b536d44865c1dd807f2aa030
Gerrit-Change-Number: 33541
Gerrit-PatchSet: 1
Gerrit-Owner: Shivani Parekh <[email protected]>
Gerrit-MessageType: newchange
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