Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34982 )
Change subject: arch-sparc: Replace any getDTBPtr/getITBPtr usage
......................................................................
arch-sparc: Replace any getDTBPtr/getITBPtr usage
Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/sparc/faults.cc
M src/arch/sparc/tlb.cc
M src/arch/sparc/tlb.hh
3 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 34a0d52..3c80e52 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -669,8 +669,9 @@
// false for syscall emulation mode regardless of whether the
// address is real in preceding code. Not sure sure that this is
// correct, but also not sure if it matters at all.
- dynamic_cast<TLB *>(tc->getITBPtr())->
- insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+ static_cast<MMU *>(tc->getMMUPtr())->insertTlbEntry(
+ alignedvaddr, partition_id, context_id,
+ false, entry.pte, MMU::I_TLBS);
}
void
@@ -756,8 +757,9 @@
// false for syscall emulation mode regardless of whether the
// address is real in preceding code. Not sure sure that this is
// correct, but also not sure if it matters at all.
- dynamic_cast<TLB *>(tc->getDTBPtr())->
- insert(alignedvaddr, partition_id, context_id, false, entry.pte);
+ static_cast<MMU *>(tc->getMMUPtr())->insertTlbEntry(
+ alignedvaddr, partition_id, context_id,
+ false, entry.pte, MMU::D_TLBS);
}
void
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 2a8fdb9..4fcb42c 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -955,7 +955,7 @@
DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
(uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
- TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+ TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
switch (asi) {
case ASI_LSU_CONTROL_REG:
@@ -1151,7 +1151,7 @@
DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
(uint32_t)asi, va, data);
- TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+ TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
switch (asi) {
case ASI_LSU_CONTROL_REG:
@@ -1388,7 +1388,7 @@
TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
{
uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
- TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
+ TLB *itb = static_cast<TLB *>(tc->getMMUPtr()->itb);
ptrs[0] = MakeTsbPtr(Ps0, tag_access,
c0_tsb_ps0,
c0_config,
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index bdda832..25dba3b 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -51,8 +51,7 @@
class TLB : public BaseTLB
{
// These faults need to be able to populate the tlb in SE mode.
- friend class FastInstructionAccessMMUMiss;
- friend class FastDataAccessMMUMiss;
+ friend class MMU;
// TLB state
protected:
@@ -204,6 +203,20 @@
{
public:
MMU(const SparcMMUParams *p);
+
+ void
+ insertTlbEntry(Addr vpn, int partition_id, int context_id, bool real,
+ const PageTableEntry& PTE, TLBType tlbs, int entry = -1)
+ {
+ if (tlbs & TLBType::I_TLBS) {
+ static_cast<TLB*>(itb)->insert(vpn, partition_id,
+ context_id, real, PTE, entry);
+ }
+ if (tlbs & TLBType::D_TLBS) {
+ static_cast<TLB*>(dtb)->insert(vpn, partition_id,
+ context_id, real, PTE, entry);
+ }
+ }
};
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Gerrit-Change-Number: 34982
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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