Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/35396 )
Change subject: dev-arm: Automate FdtProperty generation with
ArmInterruptPin
......................................................................
dev-arm: Automate FdtProperty generation with ArmInterruptPin
Change-Id: I1963bd139d8abd8988d5ceedaf85c74279546078
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/dev/arm/Gic.py
1 file changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 17a553f..a4f0e8e 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -99,11 +99,31 @@
cxx_header = "dev/arm/base_gic.hh"
cxx_class = "ArmSPIGen"
+ def generateFdtProperty(self):
+ """
+ Return a list used as an entry for an interrupt FdtProperty
+
+ Subtracting 32 because Linux assumes that SPIs start at 0, while
+ gem5 uses the internal GIC numbering (SPIs start at 32)
+ """
+ return [ 0, self.num - 32, int(self.int_type.getValue()) ]
+
class ArmPPI(ArmInterruptPin):
type = 'ArmPPI'
cxx_header = "dev/arm/base_gic.hh"
cxx_class = "ArmPPIGen"
+ def generateFdtProperty(self):
+ """
+ Return a list used as an entry for an interrupt FdtProperty
+
+ Subtracting 16 because Linux assumes that PPIs start at 0, while
+ gem5 uses the internal GIC numbering (PPIs start at 16)
+ We or the value with 0xf00 which corresponds to the following
+ Linux kernel macroes IRQ_LEVEL, IRQ_PER_CPU, IRQ_NOPROBE,
IRQ_NOREQUEST
+ """
+ return [ 1, self.num - 16, 0xf00 | int(self.int_type.getValue()) ]
+
class GicV2(BaseGic):
type = 'GicV2'
cxx_header = "dev/arm/gic_v2.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1963bd139d8abd8988d5ceedaf85c74279546078
Gerrit-Change-Number: 35396
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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