Tommaso Marinelli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36895 )
Change subject: arch-x86: Fix execution with TraceCPU
......................................................................
arch-x86: Fix execution with TraceCPU
Simulations using TraceCPU fail to execute with the x86 ISA because of
an assertion error when connecting the interrupt controller message
ports. In fact, the method getAddrRanges() of the Interrupts class
checks for the existence of a thread context, which in the case of
TraceCPU is never set. This patch simply removes the problematic
assert.
Change-Id: I07ac930292078027885cf925983bcac629303c8a
---
M src/arch/x86/interrupts.cc
1 file changed, 0 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/interrupts.cc b/src/arch/x86/interrupts.cc
index 956cd3c..1661575 100644
--- a/src/arch/x86/interrupts.cc
+++ b/src/arch/x86/interrupts.cc
@@ -343,7 +343,6 @@
AddrRangeList
X86ISA::Interrupts::getAddrRanges() const
{
- assert(tc);
AddrRangeList ranges;
ranges.push_back(RangeSize(pioAddr, PageBytes));
return ranges;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I07ac930292078027885cf925983bcac629303c8a
Gerrit-Change-Number: 36895
Gerrit-PatchSet: 1
Gerrit-Owner: Tommaso Marinelli <[email protected]>
Gerrit-MessageType: newchange
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