Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/36883 )
Change subject: x86: Convert X86 to use local reg index storage.
......................................................................
x86: Convert X86 to use local reg index storage.
Change-Id: I42bd3e08ebcffe25e2f366be82702b3c04225e92
---
M src/arch/x86/isa/formats/basic.isa
M src/arch/x86/isa/formats/monitor_mwait.isa
M src/arch/x86/isa/microops/debug.isa
M src/arch/x86/isa/microops/fpop.isa
M src/arch/x86/isa/microops/ldstop.isa
M src/arch/x86/isa/microops/limmop.isa
M src/arch/x86/isa/microops/mediaop.isa
M src/arch/x86/isa/microops/regop.isa
M src/arch/x86/isa/microops/seqop.isa
M src/arch/x86/isa/microops/specop.isa
10 files changed, 91 insertions(+), 29 deletions(-)
diff --git a/src/arch/x86/isa/formats/basic.isa
b/src/arch/x86/isa/formats/basic.isa
index cd9ec9e..32e4087 100644
--- a/src/arch/x86/isa/formats/basic.isa
+++ b/src/arch/x86/isa/formats/basic.isa
@@ -38,25 +38,29 @@
// Basic instruction class declaration template.
def template BasicDeclare {{
- /**
- * Static instruction class for "%(mnemonic)s".
- */
- class %(class_name)s : public %(base_class)s
- {
- public:
- // Constructor.
- %(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const
override;
- };
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ private:
+ %(reg_idx_arr_decl)s;
+
+ public:
+ // Constructor.
+ %(class_name)s(ExtMachInst machInst);
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ };
}};
// Basic instruction class constructor template.
def template BasicConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst)
- : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
- {
- %(constructor)s;
- }
+ %(class_name)s::%(class_name)s(ExtMachInst machInst) :
+ %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ {
+ %(set_reg_idx_arr)s;
+ %(constructor)s;
+ }
}};
// Basic instruction class execute method template.
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa
b/src/arch/x86/isa/formats/monitor_mwait.isa
index 99fc85b..2d25db1 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -47,7 +47,10 @@
def template MwaitDeclare {{
class %(class_name)s : public %(base_class)s
{
- public:
+ private:
+ %(reg_idx_arr_decl)s;
+
+ public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
diff --git a/src/arch/x86/isa/microops/debug.isa
b/src/arch/x86/isa/microops/debug.isa
index b7e3a9c..326f245 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -68,19 +68,6 @@
return response.str();
}
};
-
- class MicroDebugFlags : public MicroDebug
- {
- protected:
- uint8_t cc;
-
- public:
- MicroDebugFlags(ExtMachInst _machInst, const char *mnem,
- const char *instMnem, uint64_t setFlags,
- GenericISA::M5DebugFault *_fault, uint8_t _cc);
-
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- };
}};
output decoder {{
@@ -93,6 +80,24 @@
{}
}};
+def template MicroDebugFlagsDeclare {{
+ class %(class_name)s : public %(base_class)s
+ {
+ private:
+ %(reg_idx_arr_decl)s;
+
+ protected:
+ uint8_t cc;
+
+ public:
+ %(class_name)s(ExtMachInst _machInst, const char *mnem,
+ const char *instMnem, uint64_t setFlags,
+ GenericISA::M5DebugFault *_fault, uint8_t _cc);
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ };
+}};
+
def template MicroDebugFlagsExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
@@ -116,6 +121,7 @@
%(base_class)s(machInst, mnem, instMnem, setFlags, _fault),
cc(_cc)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -125,6 +131,8 @@
{"code": "",
"cond_test": "checkCondition(ccFlagBits | cfofBits | \
dfBit | ecfBit | ezfBit,
cc)"})
+
+ header_output = MicroDebugFlagsDeclare.subst(iop)
exec_output = MicroDebugFlagsExecute.subst(iop)
decoder_output = MicroDebugFlagsConstructor.subst(iop)
}};
diff --git a/src/arch/x86/isa/microops/fpop.isa
b/src/arch/x86/isa/microops/fpop.isa
index 7721162..238fa93 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -76,6 +76,9 @@
def template MicroFpOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -95,6 +98,7 @@
_src1, _src2, _dest, _dataSize, _spm,
%(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
diff --git a/src/arch/x86/isa/microops/ldstop.isa
b/src/arch/x86/isa/microops/ldstop.isa
index 3480137..79aadfa 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -70,6 +70,9 @@
def template MicroLeaDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -220,6 +223,9 @@
def template MicroLdStOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -241,6 +247,9 @@
def template MicroLdStSplitOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -270,6 +279,7 @@
_disp, _segment, _data,
_dataSize, _addressSize, _memFlags, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -287,6 +297,7 @@
_disp, _segment, _dataLow, _dataHi,
_dataSize, _addressSize, _memFlags, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
diff --git a/src/arch/x86/isa/microops/limmop.isa
b/src/arch/x86/isa/microops/limmop.isa
index f703133..b46be03 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -54,6 +54,9 @@
def template MicroLimmOpDeclare {{
class %(class_name)s : public X86ISA::X86MicroopBase
{
+ private:
+ %(reg_idx_arr_decl)s;
+
protected:
const RegIndex dest;
const uint64_t imm;
@@ -96,6 +99,7 @@
setFlags, %(op_class)s),
dest(_dest.index()), imm(_imm), dataSize(_dataSize)
{
+ %(set_reg_idx_arr)s;
foldOBit = (dataSize == 1 && !machInst.rex.present) ? 1 << 6 : 0;
%(constructor)s;
}
diff --git a/src/arch/x86/isa/microops/mediaop.isa
b/src/arch/x86/isa/microops/mediaop.isa
index 3078a69..bf5fc67 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -49,6 +49,9 @@
def template MediaOpRegDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -63,6 +66,9 @@
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -82,6 +88,7 @@
_src1, _src2, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -95,6 +102,7 @@
_src1, _imm8, _dest, _srcSize, _destSize, _ext,
%(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
diff --git a/src/arch/x86/isa/microops/regop.isa
b/src/arch/x86/isa/microops/regop.isa
index c00c6fa..da1f9ae 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -103,6 +103,9 @@
def template MicroRegOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -123,6 +126,9 @@
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem, uint64_t setFlags,
@@ -148,6 +154,7 @@
_src1, _src2, _dest, _dataSize, _ext,
%(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
%(cond_control_flag_init)s;
}
@@ -173,6 +180,7 @@
_src1, _imm8, _dest, _dataSize, _ext,
%(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
%(cond_control_flag_init)s;
}
diff --git a/src/arch/x86/isa/microops/seqop.isa
b/src/arch/x86/isa/microops/seqop.isa
index 22af417..64f749b 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -57,6 +57,9 @@
def template SeqOpDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
uint64_t setFlags, uint16_t _target, uint8_t _cc);
@@ -104,6 +107,7 @@
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
setFlags, _target, _cc)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
%(cond_control_flag_init)s;
}
diff --git a/src/arch/x86/isa/microops/specop.isa
b/src/arch/x86/isa/microops/specop.isa
index 1d50569..aad171a 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -77,6 +77,9 @@
def template MicroFaultDeclare {{
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst, const char * instMnem,
uint64_t setFlags, Fault _fault, uint8_t _cc);
@@ -125,6 +128,7 @@
Fault _fault, uint8_t _cc) :
%(base_class)s(machInst, instMnem, setFlags, _fault, _cc)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -209,6 +213,9 @@
def template MicroFenceOpDeclare {{
class %(class_name)s : public X86ISA::X86MicroopBase
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
%(class_name)s(ExtMachInst _machInst,
const char * instMnem,
@@ -224,6 +231,7 @@
%(base_class)s(machInst, "%(mnemonic)s", instMnem,
setFlags, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42bd3e08ebcffe25e2f366be82702b3c04225e92
Gerrit-Change-Number: 36883
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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