Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/36881 )
Change subject: riscv: Convert RISCV to use local reg index storage.
......................................................................
riscv: Convert RISCV to use local reg index storage.
This was mostly straightforward, except that the micro and macro op
classes need to be seperated for AMO classes so that the reg_idx_arr_decl
will have the right sizes.
Change-Id: Ibc0a9df0cb79924342eaceb0f09606913442f841
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36881
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/isa/formats/amo.isa
M src/arch/riscv/isa/formats/basic.isa
M src/arch/riscv/isa/formats/compressed.isa
M src/arch/riscv/isa/formats/mem.isa
M src/arch/riscv/isa/formats/standard.isa
5 files changed, 67 insertions(+), 28 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/riscv/isa/formats/amo.isa
b/src/arch/riscv/isa/formats/amo.isa
index 7d01145..cde0fd8 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -38,23 +38,31 @@
// Constructor
%(class_name)s(ExtMachInst machInst);
- protected:
-
+ protected:
/*
* The main RMW part of an AMO
*/
- class %(class_name)sRMW : public %(base_class)sMicro
- {
- public:
- // Constructor
- %(class_name)sRMW(ExtMachInst machInst, %(class_name)s *_p);
+ class %(class_name)sRMW;
+ };
+}};
- Fault execute(ExecContext *, Trace::InstRecord *) const
override;
- Fault initiateAcc(ExecContext *,
- Trace::InstRecord *) const override;
- Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
- };
+def template AtomicMemOpRMWDeclare {{
+ /*
+ * The main RMW part of an AMO
+ */
+ class %(class_name)s::%(class_name)sRMW : public %(base_class)s
+ {
+ private:
+ %(reg_idx_arr_decl)s;
+
+ public:
+ // Constructor
+ %(class_name)sRMW(ExtMachInst machInst, %(class_name)s *_p);
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
override;
+ Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
};
}};
@@ -68,20 +76,25 @@
// Constructor
%(class_name)s(ExtMachInst machInst);
- protected:
+ protected:
+ class %(class_name)sMicro;
+ };
+}};
- class %(class_name)sMicro : public %(base_class)sMicro
- {
- public:
- // Constructor
- %(class_name)sMicro(ExtMachInst machInst, %(class_name)s *_p);
+def template LRSCMicroDeclare {{
+ class %(class_name)s::%(class_name)sMicro : public %(base_class)s
+ {
+ private:
+ %(reg_idx_arr_decl)s;
- Fault execute(ExecContext *, Trace::InstRecord *) const
override;
- Fault initiateAcc(ExecContext *,
- Trace::InstRecord *) const override;
- Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
- };
+ public:
+ // Constructor
+ %(class_name)sMicro(ExtMachInst machInst, %(class_name)s *_p);
+
+ Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const
override;
+ Fault completeAcc(PacketPtr, ExecContext *,
+ Trace::InstRecord *) const override;
};
}};
@@ -141,8 +154,9 @@
def template LRSCMicroConstructor {{
%(class_name)s::%(class_name)sMicro::%(class_name)sMicro(
ExtMachInst machInst, %(class_name)s *_p)
- : %(base_class)sMicro("%(mnemonic)s", machInst, %(op_class)s)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
@@ -204,6 +218,7 @@
ExtMachInst machInst, %(class_name)s *_p)
: %(base_class)s("%(mnemonic)s[l]", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
// overwrite default flags
@@ -472,12 +487,13 @@
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- iop = InstObjParams(name, Name, 'LoadReserved',
+ iop = InstObjParams(name, Name, 'LoadReservedMicro',
{'ea_code': ea_code, 'memacc_code': memacc_code,
'postacc_code': postacc_code}, inst_flags)
iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \
'|'.join(['Request::%s' % flag for flag in mem_flags]) + ';'
+ header_output += LRSCMicroDeclare.subst(iop)
decoder_output += LRSCMicroConstructor.subst(iop)
decode_block += BasicDecode.subst(iop)
exec_output += LoadReservedExecute.subst(iop) \
@@ -499,12 +515,13 @@
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- iop = InstObjParams(name, Name, 'StoreCond',
+ iop = InstObjParams(name, Name, 'StoreCondMicro',
{'ea_code': ea_code, 'memacc_code': memacc_code,
'postacc_code': postacc_code}, inst_flags)
iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \
'|'.join(['Request::%s' % flag for flag in mem_flags]) + ';'
+ header_output += LRSCMicroDeclare.subst(iop)
decoder_output += LRSCMicroConstructor.subst(iop)
decode_block += BasicDecode.subst(iop)
exec_output += StoreCondExecute.subst(iop) \
@@ -536,6 +553,7 @@
rmw_iop.constructor += '\n\tmemAccessFlags = memAccessFlags | ' + \
'|'.join(['Request::%s' % flag for flag in rmw_mem_flags]) + ';'
+ header_output += AtomicMemOpRMWDeclare.subst(rmw_iop)
decoder_output += AtomicMemOpRMWConstructor.subst(rmw_iop)
decode_block += BasicDecode.subst(rmw_iop)
exec_output += AtomicMemOpRMWExecute.subst(rmw_iop) \
diff --git a/src/arch/riscv/isa/formats/basic.isa
b/src/arch/riscv/isa/formats/basic.isa
index 1c597e8..4b9f6c9 100644
--- a/src/arch/riscv/isa/formats/basic.isa
+++ b/src/arch/riscv/isa/formats/basic.isa
@@ -34,6 +34,9 @@
//
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
/// Constructor.
%(class_name)s(MachInst machInst);
@@ -47,6 +50,7 @@
%(class_name)s::%(class_name)s(MachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
}
}};
diff --git a/src/arch/riscv/isa/formats/compressed.isa
b/src/arch/riscv/isa/formats/compressed.isa
index b970912..ad73383 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -120,6 +120,9 @@
//
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
/// Constructor.
%(class_name)s(MachInst machInst);
diff --git a/src/arch/riscv/isa/formats/mem.isa
b/src/arch/riscv/isa/formats/mem.isa
index faaae6f..1dd9dc2 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -37,6 +37,9 @@
*/
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
@@ -53,6 +56,7 @@
%(class_name)s::%(class_name)s(ExtMachInst machInst):
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
%(offset_code)s;
}
diff --git a/src/arch/riscv/isa/formats/standard.isa
b/src/arch/riscv/isa/formats/standard.isa
index 04a469f..72f7dc1 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -39,6 +39,9 @@
//
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
/// Constructor.
%(class_name)s(MachInst machInst);
@@ -52,6 +55,7 @@
%(class_name)s::%(class_name)s(MachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
+ %(set_reg_idx_arr)s;
%(constructor)s;
%(imm_code)s;
}
@@ -177,6 +181,9 @@
//
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
/// Constructor.
%(class_name)s(MachInst machInst);
@@ -237,6 +244,9 @@
//
class %(class_name)s : public %(base_class)s
{
+ private:
+ %(reg_idx_arr_decl)s;
+
public:
/// Constructor.
%(class_name)s(MachInst machInst);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibc0a9df0cb79924342eaceb0f09606913442f841
Gerrit-Change-Number: 36881
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Daniel Carvalho <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Ian Jiang <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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