Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/38388 )
Change subject: cpu: Track misc regs in vectors in the O3 CPU instruction
class.
......................................................................
cpu: Track misc regs in vectors in the O3 CPU instruction class.
Most instructions won't actually write to misc regs, so the overhead
should be quite small, particularlly compared to the other overheads in
the O3.
Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
---
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
2 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index c2016e5..04831e3 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -100,17 +100,13 @@
using BaseDynInst<Impl>::_destRegIdx;
/** Values to be written to the destination misc. registers. */
- std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
+ std::vector<RegVal> _destMiscRegVal;
/** Indexes of the destination misc. registers. They are needed to
defer
* the write accesses to the misc. registers until the commit stage,
when
* the instruction is out of its speculative state.
*/
- std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
-
- /** Number of destination misc. registers. */
- uint8_t _numDestMiscRegs;
-
+ std::vector<short> _destMiscRegIdx;
public:
#if TRACING_ON
@@ -146,17 +142,13 @@
* committed instead of making a new entry. If not, make a new
* entry and record the write.
*/
- for (int idx = 0; idx < _numDestMiscRegs; idx++) {
- if (_destMiscRegIdx[idx] == misc_reg) {
- _destMiscRegVal[idx] = val;
- return;
- }
+ for (auto &idx: _destMiscRegIdx) {
+ if (idx == misc_reg)
+ return;
}
- assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
- _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
- _destMiscRegVal[_numDestMiscRegs] = val;
- _numDestMiscRegs++;
+ _destMiscRegIdx.push_back(misc_reg);
+ _destMiscRegVal.push_back(val);
}
/** Reads a misc. register, including any side-effects the read
@@ -192,7 +184,7 @@
bool no_squash_from_TC = this->thread->noSquashFromTC;
this->thread->noSquashFromTC = true;
- for (int i = 0; i < _numDestMiscRegs; i++)
+ for (int i = 0; i < _destMiscRegIdx.size(); i++)
this->cpu->setMiscReg(
_destMiscRegIdx[i], _destMiscRegVal[i],
this->threadNumber);
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 47ec260..adb9447 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -107,8 +107,6 @@
std::fill(this->_readySrcRegIdx.begin(), this->_readySrcRegIdx.end(),
false);
- _numDestMiscRegs = 0;
-
#if TRACING_ON
// Value -1 indicates that particular phase
// hasn't happened (yet).
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38388
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
Gerrit-Change-Number: 38388
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
