Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/38388 )
Change subject: cpu: Track misc regs in vectors in the O3 CPU instruction
class.
......................................................................
cpu: Track misc regs in vectors in the O3 CPU instruction class.
Most instructions won't actually write to misc regs, so the overhead
should be quite small, particularlly compared to the other overheads in
the O3.
Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38388
Tested-by: kokoro <[email protected]>
Reviewed-by: Giacomo Travaglini <[email protected]>
Maintainer: Giacomo Travaglini <[email protected]>
---
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
2 files changed, 8 insertions(+), 18 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index b89b3c7..f084368 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -93,17 +93,13 @@
using BaseDynInst<Impl>::cpu;
/** Values to be written to the destination misc. registers. */
- std::array<RegVal, TheISA::MaxMiscDestRegs> _destMiscRegVal;
+ std::vector<RegVal> _destMiscRegVal;
/** Indexes of the destination misc. registers. They are needed to
defer
* the write accesses to the misc. registers until the commit stage,
when
* the instruction is out of its speculative state.
*/
- std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
-
- /** Number of destination misc. registers. */
- uint8_t _numDestMiscRegs;
-
+ std::vector<short> _destMiscRegIdx;
public:
#if TRACING_ON
@@ -139,17 +135,13 @@
* committed instead of making a new entry. If not, make a new
* entry and record the write.
*/
- for (int idx = 0; idx < _numDestMiscRegs; idx++) {
- if (_destMiscRegIdx[idx] == misc_reg) {
- _destMiscRegVal[idx] = val;
- return;
- }
+ for (auto &idx: _destMiscRegIdx) {
+ if (idx == misc_reg)
+ return;
}
- assert(_numDestMiscRegs < TheISA::MaxMiscDestRegs);
- _destMiscRegIdx[_numDestMiscRegs] = misc_reg;
- _destMiscRegVal[_numDestMiscRegs] = val;
- _numDestMiscRegs++;
+ _destMiscRegIdx.push_back(misc_reg);
+ _destMiscRegVal.push_back(val);
}
/** Reads a misc. register, including any side-effects the read
@@ -185,7 +177,7 @@
bool no_squash_from_TC = this->thread->noSquashFromTC;
this->thread->noSquashFromTC = true;
- for (int i = 0; i < _numDestMiscRegs; i++)
+ for (int i = 0; i < _destMiscRegIdx.size(); i++)
this->cpu->setMiscReg(
_destMiscRegIdx[i], _destMiscRegVal[i],
this->threadNumber);
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index d960ad0..07131c3 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -106,8 +106,6 @@
{
this->regs.init();
- _numDestMiscRegs = 0;
-
#if TRACING_ON
// Value -1 indicates that particular phase
// hasn't happened (yet).
The change was submitted with unreviewed changes in the following files:
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/38388
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I840d6002cc8151f91611cfcbe2bfa52acc284c0f
Gerrit-Change-Number: 38388
Gerrit-PatchSet: 9
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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