[gem5-dev] Change in gem5/gem5[develop]: cpu: Replace fixed sized arrays in the O3 inst with vectors.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/38384 )

Change subject: cpu: Replace fixed sized arrays in the O3 inst with vectors.
......................................................................

cpu: Replace fixed sized arrays in the O3 inst with vectors.

O3 is slow enough that using vectors vs. arrays won't make a meaningful
difference, and only allocating the amount of storage we need may even
help performance slightly.

Change-Id: Id2c42869cba944deb97da01ca9e0e70186e22532
---
M src/cpu/base_dyn_inst.hh
M src/cpu/base_dyn_inst_impl.hh
M src/cpu/o3/dyn_inst.hh
M src/cpu/o3/dyn_inst_impl.hh
4 files changed, 16 insertions(+), 18 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 9fe5b53..d10d01e 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -92,11 +92,6 @@
     // The list of instructions iterator type.
     typedef typename std::list<DynInstPtr>::iterator ListIt;

-    enum {
-        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
-    };
-
   protected:
     enum Status {
         IqEntry,                 /// Instruction is in the IQ
@@ -186,7 +181,7 @@
      /** Whether or not the source register is ready.
      *  @todo: Not sure this should be here vs the derived class.
      */
-    std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
+    std::vector<bool> _readySrcRegIdx;

   public:
     /** The thread this instruction is from. */
@@ -251,22 +246,22 @@
     /** Flattened register index of the destination registers of this
      *  instruction.
      */
-    std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
+    std::vector<RegId> _flatDestRegIdx;

     /** Physical register index of the destination registers of this
      *  instruction.
      */
-    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
+    std::vector<PhysRegIdPtr> _destRegIdx;

     /** Physical register index of the source registers of this
      *  instruction.
      */
-    std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
+    std::vector<PhysRegIdPtr> _srcRegIdx;

     /** Physical register index of the previous producers of the
      *  architected destinations.
      */
-    std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
+    std::vector<PhysRegIdPtr> _prevDestRegIdx;


   public:
@@ -368,7 +363,7 @@
     PhysRegIdPtr
     renamedSrcRegIdx(int idx) const
     {
-        assert(TheISA::MaxInstSrcRegs > idx);
+        assert(_srcRegIdx.size() > idx);
         return _srcRegIdx[idx];
     }

diff --git a/src/cpu/base_dyn_inst_impl.hh b/src/cpu/base_dyn_inst_impl.hh
index bfe8ff5..c2e4222 100644
--- a/src/cpu/base_dyn_inst_impl.hh
+++ b/src/cpu/base_dyn_inst_impl.hh
@@ -64,10 +64,15 @@
   : staticInst(_staticInst), cpu(cpu),
     thread(nullptr),
     traceData(nullptr),
+    _readySrcRegIdx(_staticInst->numSrcRegs()),
     macroop(_macroop),
     memData(nullptr),
     savedReq(nullptr),
-    reqToVerify(nullptr)
+    reqToVerify(nullptr),
+    _flatDestRegIdx(_staticInst->numDestRegs()),
+    _destRegIdx(_staticInst->numDestRegs()),
+    _srcRegIdx(_staticInst->numSrcRegs()),
+    _prevDestRegIdx(_staticInst->numDestRegs())
 {
     seqNum = seq_num;

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 8172b9a..c2016e5 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -68,11 +68,6 @@
     static constexpr auto NumVecElemPerVecReg =  
TheISA::NumVecElemPerVecReg;
     using VecPredRegContainer = TheISA::VecPredRegContainer;

-    enum {
-        MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
-    };
-
   public:
     /** BaseDynInst constructor given a binary instruction. */
     BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 6c6625c..47ec260 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -41,6 +41,8 @@
 #ifndef __CPU_O3_DYN_INST_IMPL_HH__
 #define __CPU_O3_DYN_INST_IMPL_HH__

+#include <algorithm>
+
 #include "cpu/o3/dyn_inst.hh"
 #include "debug/O3PipeView.hh"

@@ -102,7 +104,8 @@
 void
 BaseO3DynInst<Impl>::initVars()
 {
-    this->_readySrcRegIdx.reset();
+    std::fill(this->_readySrcRegIdx.begin(), this->_readySrcRegIdx.end(),
+            false);

     _numDestMiscRegs = 0;


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id2c42869cba944deb97da01ca9e0e70186e22532
Gerrit-Change-Number: 38384
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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