Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/39636 )
Change subject: configs: Do not assume single mem range in RealView
......................................................................
configs: Do not assume single mem range in RealView
The SimpleSystem was assuming a single memory range for RealView
platforms by selecting the first element of the list only:
mem_range = self.realview._mem_regions[0]
This patch is fixing this by evaluating the entire list of platform
ranges.
Change-Id: I453fff7857966076c1419b95ddb9177e51d9f8d5
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M configs/example/arm/devices.py
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index 9ef4d70..3b55be8 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2016-2017, 2019 ARM Limited
+# Copyright (c) 2016-2017, 2019, 2021 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -312,21 +312,39 @@
# CPUs->PIO
self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM
- mem_range = self.realview._mem_regions[0]
- assert int(mem_range.size()) >= int(Addr(mem_size))
- self.mem_ranges = [
- AddrRange(start=mem_range.start, size=mem_size) ]
+ self.memoryRanges(int(Addr(mem_size)))
self._caches = caches
if self._caches:
- self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
+ self.iocache = IOCache(addr_ranges=self.mem_ranges)
else:
- self.dmabridge = Bridge(delay='50ns',
- ranges=[self.mem_ranges[0]])
+ self.dmabridge = Bridge(delay='50ns',
ranges=self.mem_ranges)
self._clusters = []
self._num_cpus = 0
+ def memoryRanges(self, mem_size):
+ """
+ Define system memory ranges. This depends on the physical
+ memory map provided by the realview platform and by the memory
+ size provided by the user (mem_size argument).
+ The method is iterating over all platform ranges until they
cover
+ the entire user's memory requirements.
+ """
+ self.mem_ranges = []
+ for mem_range in self.realview._mem_regions:
+ if int(mem_range.size()) >= mem_size:
+ # The platform range is bigger than selected mem size
+ # We can stop iterating
+ self.mem_ranges.append(
+ AddrRange(start=mem_range.start, size=mem_size))
+ mem_size = 0
+ break
+ else:
+ self.mem_ranges.append(mem_range)
+ mem_size -= mem_range.size()
+ assert mem_size == 0
+
def attach_pci(self, dev):
self.realview.attachPciDevice(dev, self.iobus)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I453fff7857966076c1419b95ddb9177e51d9f8d5
Gerrit-Change-Number: 39636
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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