Matt Sinclair has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40195 )
Change subject: arch-x86: Make JRCXZ instruction do 64-bit jump
......................................................................
arch-x86: Make JRCXZ instruction do 64-bit jump
Per the AMD64 Architecture Programming Manual:
The size of the count register (CX, ECX, or RCX) depends on the
address-size attribute of the JrCXZ instruction. Therefore, JRCXZ can
only be executed in 64-bit mode
and
In 64-bit mode, the operand size defaults to 64 bits. The processor
sign-extends the 8-bit displacement value to 64 bits before adding it
to the RIP.
This patch also renames the instruction from JRCX to JRCXZ to match the
language in the programming manual.
Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40195
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/x86/isa/decoder/one_byte_opcodes.isa
M
src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
2 files changed, 4 insertions(+), 2 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index b5f77cd..04b3adc 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -483,7 +483,7 @@
0x0: LOOPNE(Jb);
0x1: LOOPE(Jb);
0x2: LOOP(Jb);
- 0x3: JRCX(Jb);
+ 0x3: JRCXZ(Jb);
0x4: IN(rAb,Ib);
0x5: IN(rAv,Iv);
0x6: OUT(Ib,rAb);
diff --git
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
index 390a08b..d0fa31a 100644
---
a/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
+++
b/src/arch/x86/isa/insts/general_purpose/control_transfer/conditional_jump.py
@@ -210,8 +210,10 @@
wrip t1, t2, flags=(nCOF,)
};
-def macroop JRCX_I
+def macroop JRCXZ_I
{
+ # Make the default data size of jumps 64 bits in 64 bit mode
+ .adjust_env oszIn64Override
.control_direct
rdip t1
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id55147d0602ff41ad6aaef483bef722ff56cae62
Gerrit-Change-Number: 40195
Gerrit-PatchSet: 3
Gerrit-Owner: Kyle Roarty <kyleroarty1...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Alexandru Duțu <alexandru.d...@amd.com>
Gerrit-CC: Jason Lowe-Power <power...@gmail.com>
Gerrit-CC: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: merged
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