Peter Yuen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40596 )
Change subject: arch-riscv: Added PMA support for RiscvTLB
......................................................................
arch-riscv: Added PMA support for RiscvTLB
Since the RISC-V privileged specs V1.11 did not specify
an implementation of physical memory attributes (PMA), e.g.
cacheability, an abstract PMA class is created. This
class acts as a container storing the PMAs.
The TLB finds the PMA defined at the system level by
Parent.any.
Change-Id: I4400133895be44da67536d80b82422ec3a49d786
---
A src/arch/riscv/RiscvPMA.py
M src/arch/riscv/RiscvTLB.py
M src/arch/riscv/SConscript
A src/arch/riscv/pma.cc
A src/arch/riscv/pma.hh
M src/arch/riscv/tlb.cc
M src/arch/riscv/tlb.hh
7 files changed, 217 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/RiscvPMA.py b/src/arch/riscv/RiscvPMA.py
new file mode 100644
index 0000000..8ab67ab
--- /dev/null
+++ b/src/arch/riscv/RiscvPMA.py
@@ -0,0 +1,46 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2021 Huawei International
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.proxy import *
+
+
+class PMA(SimObject):
+ type = 'PMA'
+ cxx_header = 'arch/riscv/pma.hh'
+ uncacheable = VectorParam.AddrRange([], "Uncacheable address ranges")
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index 4844feb..a1f7e03 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -2,6 +2,7 @@
# Copyright (c) 2007 MIPS Technologies, Inc.
# Copyright (c) 2020 Barkhausen Institut
+# Copyright (c) 2021 Huawei International
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -49,3 +50,7 @@
size = Param.Int(64, "TLB size")
walker = Param.RiscvPagetableWalker(\
RiscvPagetableWalker(), "page table walker")
+ # The pma is found under the System object
+ # defining PMA under the Platform object might not work
+ # as the CPU and MMU are not children of the Platform
+ pma = Param.PMA(Parent.any, "Physical Memory Attributes")
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 472264f..ae0b438 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -54,6 +54,7 @@
Source('reg_abi.cc')
Source('remote_gdb.cc')
Source('tlb.cc')
+ Source('pma.cc')
Source('linux/se_workload.cc')
Source('linux/linux.cc')
@@ -64,6 +65,7 @@
SimObject('RiscvInterrupts.py')
SimObject('RiscvISA.py')
SimObject('RiscvMMU.py')
+ SimObject('RiscvPMA.py')
SimObject('RiscvSeWorkload.py')
SimObject('RiscvTLB.py')
diff --git a/src/arch/riscv/pma.cc b/src/arch/riscv/pma.cc
new file mode 100644
index 0000000..a41e912
--- /dev/null
+++ b/src/arch/riscv/pma.cc
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/riscv/pma.hh"
+
+#include "base/addr_range.hh"
+#include "mem/packet.hh"
+#include "params/PMA.hh"
+#include "sim/sim_object.hh"
+
+PMA::PMA(const Params ¶ms) :
+SimObject(params),
+uncacheable(params.uncacheable.begin(), params.uncacheable.end())
+{
+}
+
+bool
+PMA::isUncacheable(const AddrRange &range)
+{
+ for (auto const &uncacheable_range: uncacheable) {
+ if (range.isSubset(uncacheable_range)) {
+ return true;
+ }
+ }
+ return false;
+}
+
+bool
+PMA::isUncacheable(const Addr &addr, const unsigned size)
+{
+ AddrRange range(addr, addr + size);
+ return isUncacheable(range);
+}
+
+bool
+PMA::isUncacheable(PacketPtr pkt)
+{
+ return isUncacheable(pkt->getAddrRange());
+}
diff --git a/src/arch/riscv/pma.hh b/src/arch/riscv/pma.hh
new file mode 100644
index 0000000..38bbb57
--- /dev/null
+++ b/src/arch/riscv/pma.hh
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2021 Huawei International
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_RISCV_PMA_HH__
+#define __ARCH_RISCV_PMA_HH__
+
+#include "base/addr_range.hh"
+#include "mem/packet.hh"
+#include "params/PMA.hh"
+#include "sim/sim_object.hh"
+
+/**
+ * Based on the RISC-V ISA privileged specifications
+ * V1.11, there is no implementation guidelines on the
+ * Physical Memory Attributes (PMA).
+ *
+ * This container class intends to provide an interface
+ * for the TLB to fetch the memory attributes of each
+ * address range and perform the necessary actions.
+ */
+
+class PMA : public SimObject
+{
+ public:
+ typedef PMAParams Params;
+
+ const Params &
+ params() const
+ {
+ return dynamic_cast<const Params &>(_params);
+ }
+ PMA(const Params ¶ms);
+
+ AddrRangeList uncacheable;
+
+ bool isUncacheable(const AddrRange &range);
+ bool isUncacheable(const Addr &addr, const unsigned size);
+ bool isUncacheable(PacketPtr pkt);
+
+};
+
+#endif // __ARCH_RISCV_PMA_HH__
diff --git a/src/arch/riscv/tlb.cc b/src/arch/riscv/tlb.cc
index 491f15f..2a7561b 100644
--- a/src/arch/riscv/tlb.cc
+++ b/src/arch/riscv/tlb.cc
@@ -2,6 +2,7 @@
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2020 Barkhausen Institut
+ * Copyright (c) 2021 Huawei International
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -38,6 +39,7 @@
#include "arch/riscv/mmu.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/pagetable_walker.hh"
+#include "arch/riscv/pma.hh"
#include "arch/riscv/pra_constants.hh"
#include "arch/riscv/utility.hh"
#include "base/inifile.hh"
@@ -65,8 +67,9 @@
return (static_cast<Addr>(asid) << 48) | vpn;
}
-TLB::TLB(const Params &p)
- : BaseTLB(p), size(p.size), tlb(size), lruSeq(0), stats(this)
+TLB::TLB(const Params &p) :
+ BaseTLB(p), size(p.size), tlb(size),
+ lruSeq(0), stats(this), pma(p.pma)
{
for (size_t x = 0; x < size; x++) {
tlb[x].trieHandle = NULL;
@@ -361,6 +364,12 @@
fault = std::make_shared<AddressFault>(req->getVaddr(), code);
}
+ if (!delayed && fault == NoFault) {
+ if (pma->isUncacheable(req->getPaddr(), req->getSize())) {
+ req->setFlags(Request::UNCACHEABLE);
+ }
+ }
+
return fault;
} else {
// In the O3 CPU model, sometimes a memory access will be
speculatively
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index cb6059e..46c5dd6 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -2,6 +2,7 @@
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2020 Barkhausen Institut
+ * Copyright (c) 2021 Huawei International
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,6 +38,7 @@
#include "arch/riscv/isa.hh"
#include "arch/riscv/isa_traits.hh"
#include "arch/riscv/pagetable.hh"
+#include "arch/riscv/pma.hh"
#include "arch/riscv/utility.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
@@ -81,6 +83,8 @@
Stats::Formula accesses;
} stats;
+ PMA *pma;
+
public:
typedef RiscvTLBParams Params;
TLB(const Params &p);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4400133895be44da67536d80b82422ec3a49d786
Gerrit-Change-Number: 40596
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Yuen <[email protected]>
Gerrit-MessageType: newchange
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