Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40889 )
Change subject: arch-power: Add TAR and associated instructions
......................................................................
arch-power: Add TAR and associated instructions
This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it.
* Move To Target Address Register (mttar)
* Move From Target Address Register (mftar)
* Branch Conditional to Branch Target Address Register (bctar[l])
Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/operands.isa
M src/arch/power/miscregs.hh
4 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 9355198..5ecb8cc 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -49,12 +49,14 @@
!myMnemonic.compare("mtxer") ||
!myMnemonic.compare("mtlr") ||
!myMnemonic.compare("mtctr") ||
- !myMnemonic.compare("cmpi")) {
+ !myMnemonic.compare("cmpi") ||
+ !myMnemonic.compare("mttar")) {
printDest = false;
} else if (!myMnemonic.compare("mfcr") ||
!myMnemonic.compare("mfxer") ||
!myMnemonic.compare("mflr") ||
- !myMnemonic.compare("mfctr")) {
+ !myMnemonic.compare("mfctr") ||
+ !myMnemonic.compare("mftar")) {
printSrcs = false;
}
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index a58e947..4005da8 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -56,6 +56,7 @@
format BranchRegCondOp {
16: bclr({{ NIA = LR & -4ULL; }}, true, [ IsReturn ]);
528: bcctr({{ NIA = CTR & -4ULL; }});
+ 560: bctar({{ NIA = TAR & -4ULL; }}, true);
}
// Condition register manipulation instructions.
@@ -518,12 +519,14 @@
0x20: mfxer({{ Rt = XER; }});
0x100: mflr({{ Rt = LR; }});
0x120: mfctr({{ Rt = CTR; }});
+ 0x1f9: mftar({{ Rt = TAR; }});
}
467: decode SPR {
0x20: mtxer({{ XER = Rs; }});
0x100: mtlr({{ LR = Rs; }});
0x120: mtctr({{ CTR = Rs; }});
+ 0x1f9: mttar({{ TAR = Rs; }});
}
144: mtcrf({{
diff --git a/src/arch/power/isa/operands.isa
b/src/arch/power/isa/operands.isa
index 4ca4d24..af89a62 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -65,6 +65,7 @@
'XER': ('ControlReg', 'uw', 'MISCREG_XER', 'IsInteger', 9),
'LR': ('ControlReg', 'ud', 'MISCREG_LR', 'IsInteger', 9),
'CTR': ('ControlReg', 'ud', 'MISCREG_CTR', 'IsInteger', 9),
+ 'TAR': ('ControlReg', 'ud', 'MISCREG_TAR', 'IsInteger', 9),
# Setting as ControlReg so things are stored as an integer, not double
'FPSCR': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsFloating', 9),
diff --git a/src/arch/power/miscregs.hh b/src/arch/power/miscregs.hh
index 9d366b2..dc9e9af 100644
--- a/src/arch/power/miscregs.hh
+++ b/src/arch/power/miscregs.hh
@@ -40,6 +40,7 @@
MISCREG_XER,
MISCREG_LR,
MISCREG_CTR,
+ MISCREG_TAR,
NUM_MISCREGS
};
@@ -49,6 +50,7 @@
"XER",
"LR",
"CTR",
+ "TAR"
};
BitUnion32(Cr)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Gerrit-Change-Number: 40889
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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