Boris Shingarov has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/40889 )

Change subject: arch-power: Add TAR and associated instructions
......................................................................

arch-power: Add TAR and associated instructions

This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it.
  * Move To Target Address Register (mttar)
  * Move From Target Address Register (mftar)
  * Branch Conditional to Branch Target Address Register (bctar[l])

Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40889
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/operands.isa
M src/arch/power/regs/int.hh
4 files changed, 15 insertions(+), 5 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index fdf3b51..c10abe6 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -49,12 +49,14 @@
                myMnemonic == "mtxer" ||
                myMnemonic == "mtlr"  ||
                myMnemonic == "mtctr" ||
+               myMnemonic == "mttar" ||
                myMnemonic == "cmpi") {
         printDest = false;
     } else if (myMnemonic == "mfcr"  ||
                myMnemonic == "mfxer" ||
                myMnemonic == "mflr"  ||
-               myMnemonic == "mfctr") {
+               myMnemonic == "mfctr" ||
+               myMnemonic == "mftar") {
         printSrcs = false;
     }

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index e4f57ca..ac52ab3 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -152,8 +152,12 @@
             }});
         }

-        // Conditionally branch to address in CTR based on CR.
-        528: BranchRegCondOp::bcctr({{ NIA = CTR & -4ULL; }});
+        // Conditionally branch to an address in a register based on
+        // either CR only or both CR and CTR.
+        format BranchRegCondOp {
+            528: bcctr({{ NIA = CTR & -4ULL; }});
+            560: bctar({{ NIA = TAR & -4ULL; }}, true);
+        }
     }

     format IntRotateOp {
@@ -480,12 +484,14 @@
                         0x20: mfxer({{ Rt = XER; }});
                         0x100: mflr({{ Rt = LR; }});
                         0x120: mfctr({{ Rt = CTR; }});
+                        0x1f9: mftar({{ Rt = TAR; }});
                     }

                     467: decode SPR {
                         0x20: mtxer({{ XER = Rs; }});
                         0x100: mtlr({{ LR = Rs; }});
                         0x120: mtctr({{ CTR = Rs; }});
+                        0x1f9: mttar({{ TAR = Rs; }});
                     }

                     512: mcrxr({{
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 07415ba..23cf50b 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -64,6 +64,7 @@
     'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
     'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
     'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
+    'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9),
     'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),

     # Setting as IntReg so things are stored as an integer, not double
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index 7d63f79..2d6a16b 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -35,9 +35,9 @@
 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;

-// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
+// CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR
 // and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 9;
+const int NumIntSpecialRegs = 10;

 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;

@@ -51,6 +51,7 @@
     INTREG_XER,
     INTREG_LR,
     INTREG_CTR,
+    INTREG_TAR,
     INTREG_FPSCR,
     INTREG_RSV,
     INTREG_RSV_LEN,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I30f54ebd38b503fb6c9ba9dd74d00ccbbc0f8318
Gerrit-Change-Number: 40889
Gerrit-PatchSet: 6
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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