[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix disassembly for arithmetic instructions

[Sandipan Das (Gerrit) via gem5-dev]

Sandipan Das has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40900 )

Change subject: arch-power: Fix disassembly for arithmetic instructions
......................................................................

arch-power: Fix disassembly for arithmetic instructions

This fixes disassembly generated for integer add and subtract
arithmetic instructions based on the type of operands and the
special use cases for which the Power ISA provides extended
mnemonics.

Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
2 files changed, 117 insertions(+), 10 deletions(-)



diff --git a/src/arch/power/insts/integer.cc  
b/src/arch/power/insts/integer.cc
index 5ecb8cc..015ed72 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -91,16 +91,7 @@
 {
     std::stringstream ss;

-    // Generate the correct mnemonic
-    std::string myMnemonic(mnemonic);
-
-    // Special cases
-    if (!myMnemonic.compare("addi") && _numSrcRegs == 0) {
-        myMnemonic = "li";
-    } else if (!myMnemonic.compare("addis") && _numSrcRegs == 0) {
-        myMnemonic = "lis";
-    }
-    ccprintf(ss, "%-10s ", myMnemonic);
+    ccprintf(ss, "%-10s ", mnemonic);

     // Print the first destination only
     if (_numDestRegs > 0) {
@@ -123,6 +114,116 @@


 std::string
+IntArithOp::generateDisassembly(
+        Addr pc, const Loader::SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    bool printSecondSrc = true;
+
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Special cases
+    if (!myMnemonic.compare("addme") ||
+        !myMnemonic.compare("addze") ||
+        !myMnemonic.compare("subfme") ||
+        !myMnemonic.compare("subfze") ||
+        !myMnemonic.compare("neg")){
+        printSecondSrc = false;
+    }
+
+    // Additional characters depending on isa bits being set
+    if (oeSet) myMnemonic = myMnemonic + "o";
+    if (rcSet) myMnemonic = myMnemonic + ".";
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, destRegIdx(0));
+    }
+
+    // Print the first source register
+    if (_numSrcRegs > 0) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, srcRegIdx(0));
+
+        // Print the second source register
+        if (_numSrcRegs > 1 && printSecondSrc) {
+            ss << ", ";
+            printReg(ss, srcRegIdx(1));
+        }
+    }
+
+    return ss.str();
+}
+
+
+std::string
+IntImmArithOp::generateDisassembly(
+        Addr pc, const Loader::SymbolTable *symtab) const
+{
+    std::stringstream ss;
+    bool negateSimm = false;
+
+    // Generate the correct mnemonic
+    std::string myMnemonic(mnemonic);
+
+    // Special cases
+    if (!myMnemonic.compare("addi")) {
+        if (_numSrcRegs == 0) {
+            myMnemonic = "li";
+        } else if (simm < 0) {
+            myMnemonic = "subi";
+            negateSimm = true;
+        }
+    } else if (!myMnemonic.compare("addis")) {
+        if (_numSrcRegs == 0) {
+            myMnemonic = "lis";
+        } else if (simm < 0) {
+            myMnemonic = "subis";
+            negateSimm = true;
+        }
+    } else if (!myMnemonic.compare("addic") && simm < 0) {
+        myMnemonic = "subic";
+        negateSimm = true;
+    } else if (!myMnemonic.compare("addic_")) {
+        if (simm < 0) {
+            myMnemonic = "subic.";
+            negateSimm = true;
+        } else {
+            myMnemonic = "addic.";
+        }
+    }
+
+    ccprintf(ss, "%-10s ", myMnemonic);
+
+    // Print the first destination only
+    if (_numDestRegs > 0) {
+        printReg(ss, destRegIdx(0));
+    }
+
+    // Print the source register
+    if (_numSrcRegs > 0) {
+        if (_numDestRegs > 0) {
+            ss << ", ";
+        }
+        printReg(ss, srcRegIdx(0));
+    }
+
+    // Print the immediate value
+    if (negateSimm) {
+        ss << ", " << -simm;
+    } else {
+        ss << ", " << simm;
+    }
+
+    return ss.str();
+}
+
+
+std::string
 IntShiftOp::generateDisassembly(
         Addr pc, const Loader::SymbolTable *symtab) const
 {
diff --git a/src/arch/power/insts/integer.hh  
b/src/arch/power/insts/integer.hh
index 9efda43..32c1ccd 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -153,6 +153,9 @@
       : IntOp(mnem, _machInst, __opClass)
     {
     }
+
+    std::string generateDisassembly(
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };


@@ -171,6 +174,9 @@
         simm((int16_t)machInst.si)
     {
     }
+
+    std::string generateDisassembly(
+            Addr pc, const Loader::SymbolTable *symtab) const override;
 };



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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Gerrit-Change-Number: 40900
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-MessageType: newchange
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