Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40900 )
Change subject: arch-power: Fix disassembly for arithmetic instructions
......................................................................
arch-power: Fix disassembly for arithmetic instructions
This fixes disassembly generated for integer add and subtract
arithmetic instructions based on the type of operands and the
special use cases for which the Power ISA provides extended
mnemonics.
Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40900
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/insts/integer.hh
2 files changed, 122 insertions(+), 26 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 7da5bf5..2035b5c 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -68,15 +68,13 @@
ccprintf(ss, "%-10s ", myMnemonic);
// Print the first destination only
- if (_numDestRegs > 0 && printDest) {
+ if (_numDestRegs > 0 && printDest)
printReg(ss, destRegIdx(0));
- }
// Print the (possibly) two source registers
if (_numSrcRegs > 0 && printSrcs) {
- if (_numDestRegs > 0 && printDest) {
+ if (_numDestRegs > 0 && printDest)
ss << ", ";
- }
printReg(ss, srcRegIdx(0));
if (_numSrcRegs > 1 && printSecondSrc) {
ss << ", ";
@@ -93,27 +91,16 @@
{
std::stringstream ss;
- // Generate the correct mnemonic
- std::string myMnemonic(mnemonic);
-
- // Special cases
- if (!myMnemonic.compare("addi") && _numSrcRegs == 0) {
- myMnemonic = "li";
- } else if (!myMnemonic.compare("addis") && _numSrcRegs == 0) {
- myMnemonic = "lis";
- }
- ccprintf(ss, "%-10s ", myMnemonic);
+ ccprintf(ss, "%-10s ", mnemonic);
// Print the first destination only
- if (_numDestRegs > 0) {
+ if (_numDestRegs > 0)
printReg(ss, destRegIdx(0));
- }
// Print the source register
if (_numSrcRegs > 0) {
- if (_numDestRegs > 0) {
+ if (_numDestRegs > 0)
ss << ", ";
- }
printReg(ss, srcRegIdx(0));
}
@@ -125,6 +112,113 @@
std::string
+IntArithOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ bool printSecondSrc = true;
+
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (myMnemonic == "addme" ||
+ myMnemonic == "addze" ||
+ myMnemonic == "subfme" ||
+ myMnemonic == "subfze" ||
+ myMnemonic == "neg") {
+ printSecondSrc = false;
+ }
+
+ // Additional characters depending on isa bits being set
+ if (oe)
+ myMnemonic = myMnemonic + "o";
+ if (rc)
+ myMnemonic = myMnemonic + ".";
+ ccprintf(ss, "%-10s ", myMnemonic);
+
+ // Print the first destination only
+ if (_numDestRegs > 0)
+ printReg(ss, destRegIdx(0));
+
+ // Print the first source register
+ if (_numSrcRegs > 0) {
+ if (_numDestRegs > 0)
+ ss << ", ";
+ printReg(ss, srcRegIdx(0));
+
+ // Print the second source register
+ if (_numSrcRegs > 1 && printSecondSrc) {
+ ss << ", ";
+ printReg(ss, srcRegIdx(1));
+ }
+ }
+
+ return ss.str();
+}
+
+
+std::string
+IntImmArithOp::generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const
+{
+ std::stringstream ss;
+ bool negateImm = false;
+
+ // Generate the correct mnemonic
+ std::string myMnemonic(mnemonic);
+
+ // Special cases
+ if (myMnemonic == "addi") {
+ if (_numSrcRegs == 0) {
+ myMnemonic = "li";
+ } else if (si < 0) {
+ myMnemonic = "subi";
+ negateImm = true;
+ }
+ } else if (myMnemonic == "addis") {
+ if (_numSrcRegs == 0) {
+ myMnemonic = "lis";
+ } else if (si < 0) {
+ myMnemonic = "subis";
+ negateImm = true;
+ }
+ } else if (myMnemonic == "addic" && si < 0) {
+ myMnemonic = "subic";
+ negateImm = true;
+ } else if (myMnemonic == "addic_") {
+ if (si < 0) {
+ myMnemonic = "subic.";
+ negateImm = true;
+ } else {
+ myMnemonic = "addic.";
+ }
+ }
+
+ ccprintf(ss, "%-10s ", myMnemonic);
+
+ // Print the first destination only
+ if (_numDestRegs > 0)
+ printReg(ss, destRegIdx(0));
+
+ // Print the source register
+ if (_numSrcRegs > 0) {
+ if (_numDestRegs > 0)
+ ss << ", ";
+ printReg(ss, srcRegIdx(0));
+ }
+
+ // Print the immediate value
+ if (negateImm)
+ ss << ", " << -si;
+ else
+ ss << ", " << si;
+
+ return ss.str();
+}
+
+
+std::string
IntShiftOp::generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const
{
@@ -133,15 +227,13 @@
ccprintf(ss, "%-10s ", mnemonic);
// Print the first destination only
- if (_numDestRegs > 0) {
+ if (_numDestRegs > 0)
printReg(ss, destRegIdx(0));
- }
// Print the first source register
if (_numSrcRegs > 0) {
- if (_numDestRegs > 0) {
+ if (_numDestRegs > 0)
ss << ", ";
- }
printReg(ss, srcRegIdx(0));
}
@@ -161,15 +253,13 @@
ccprintf(ss, "%-10s ", mnemonic);
// Print the first destination only
- if (_numDestRegs > 0) {
+ if (_numDestRegs > 0)
printReg(ss, destRegIdx(0));
- }
// Print the first source register
if (_numSrcRegs > 0) {
- if (_numDestRegs > 0) {
+ if (_numDestRegs > 0)
ss << ", ";
- }
printReg(ss, srcRegIdx(0));
}
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index a25e65c..daef626 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -133,6 +133,9 @@
: IntOp(mnem, _machInst, __opClass)
{
}
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
};
@@ -151,6 +154,9 @@
si(sext<16>(machInst.si))
{
}
+
+ std::string generateDisassembly(
+ Addr pc, const Loader::SymbolTable *symtab) const override;
};
6 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I89b8271994e4d4b7b16efad170af5eeb5ee1aa10
Gerrit-Change-Number: 40900
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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