Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40912 )
Change subject: arch-power: Refactor compare instructions
......................................................................
arch-power: Refactor compare instructions
This changes the base class for integer compare instructions
and adds two new classes that are used to distinguish between
instructions using different operand types, i.e. register or
immediate, and comparison types, i.e. signed or unsigned. The
formats have also been updated to make use of the new base
classes.
Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Signed-off-by: Sandipan Das <[email protected]>
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
3 files changed, 118 insertions(+), 16 deletions(-)
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 38c0dd0..75d4543 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -427,6 +427,62 @@
/**
+ * Class for integer compare operations.
+ */
+class IntCompOp : public IntOp
+{
+ protected:
+
+ uint32_t length;
+ uint32_t field;
+
+ /// Constructor
+ IntCompOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntOp(mnem, _machInst, __opClass),
+ length(machInst.l),
+ field(machInst.bf)
+ {
+ }
+};
+
+
+/**
+ * Class for integer immediate compare operations.
+ */
+class IntImmCompOp : public IntCompOp
+{
+ protected:
+
+ int32_t simm;
+
+ /// Constructor
+ IntImmCompOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntCompOp(mnem, _machInst, __opClass),
+ simm((int16_t)machInst.si)
+ {
+ }
+};
+
+
+/**
+ * Class for integer immediate compare logical operations.
+ */
+class IntImmCompLogicOp : public IntCompOp
+{
+ protected:
+
+ uint32_t uimm;
+
+ /// Constructor
+ IntImmCompLogicOp(const char *mnem, MachInst _machInst, OpClass
__opClass)
+ : IntCompOp(mnem, _machInst, __opClass),
+ uimm(machInst.ui)
+ {
+ }
+};
+
+
+/**
* Class for integer operations with a shift.
*/
class IntShiftOp : public IntOp
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 06636a2..d623506 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -234,19 +234,18 @@
}
}
- format IntImmOp {
- 10: cmpli({{
- Xer xer = XER;
- uint32_t cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
- CR = insertCRField(CR, BF, cr);
- }});
+ format IntImmCompOp {
11: cmpi({{
- Xer xer = XER;
- uint32_t cr = makeCRField(Ra_sw, (int32_t)imm, xer.so);
- CR = insertCRField(CR, BF, cr);
+ cr = makeCRField(Ra_sw, (int32_t)simm, xer.so);
}});
}
+ format IntImmCompLogicOp {
+ 10: cmpli({{
+ cr = makeCRField(Ra, (uint32_t)uimm, xer.so);
+ }});
+ }
+
format IntImmLogicOp {
24: ori({{ Ra = Rs | uimm; }});
25: oris({{ Ra = Rs | (uimm << 16); }});
@@ -435,17 +434,13 @@
}});
}
- format IntOp {
+ format IntCompOp {
0: cmp({{
- Xer xer = XER;
- uint32_t cr = makeCRField(Ra_sw, Rb_sw, xer.so);
- CR = insertCRField(CR, BF, cr);
+ cr = makeCRField(Ra_sw, Rb_sw, xer.so);
}});
32: cmpl({{
- Xer xer = XER;
- uint32_t cr = makeCRField(Ra, Rb, xer.so);
- CR = insertCRField(CR, BF, cr);
+ cr = makeCRField(Ra, Rb, xer.so);
}});
}
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 6860c26..9a3e0d8 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -217,6 +217,57 @@
}};
+// Integer compare instructions.
+def format IntCompOp(code, inst_flags = []) {{
+
+ # Add code to setup variables
+ code = 'M5_VAR_USED uint32_t cr = 0;\n' + code
+ code += 'CR = insertCRField(CR, field, cr);\n'
+
+ # Add code to access XER
+ code = readXERCode + code
+
+ # Generate the class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntCompOp', code, inst_flags, BasicDecode,
+ BasicConstructor)
+}};
+
+
+// Integer immediate compare instructions.
+def format IntImmCompOp(code, inst_flags = []) {{
+
+ # Add code to setup variables
+ code = 'M5_VAR_USED uint32_t cr = 0;\n' + code
+ code += 'CR = insertCRField(CR, field, cr);\n'
+
+ # Add code to access XER
+ code = readXERCode + code
+
+ # Generate the class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntImmCompOp', code, inst_flags, BasicDecode,
+ BasicConstructor)
+}};
+
+
+// Integer immediate compare logical instructions.
+def format IntImmCompLogicOp(code, inst_flags = []) {{
+
+ # Add code to setup variables
+ code = 'M5_VAR_USED uint32_t cr = 0;\n' + code
+ code += 'CR = insertCRField(CR, field, cr);\n'
+
+ # Add code to access XER
+ code = readXERCode + code
+
+ # Generate the class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntImmCompLogicOp', code, inst_flags,
+ BasicDecode, BasicConstructor)
+}};
+
+
// Integer instructions that perform logic operations. The result is
// always written into Ra. All instructions have 2 versions depending on
// whether the Rc bit is set to compute the CR0 code. This is determined
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/40912
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Gerrit-Change-Number: 40912
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-MessageType: newchange
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