Sandipan Das has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40912 )
Change subject: arch-power: Refactor compare instructions
......................................................................
arch-power: Refactor compare instructions
This changes the base class for integer compare instructions
and adds two new classes that are used to distinguish between
instructions using different operand types, i.e. register or
immediate, and comparison types, i.e. signed or unsigned. The
formats have also been updated to make use of the new base
classes.
Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40912
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Boris Shingarov <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/insts/integer.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/integer.isa
3 files changed, 117 insertions(+), 20 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.hh
b/src/arch/power/insts/integer.hh
index 6433d85..6fb797a 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -407,6 +407,62 @@
/**
+ * Class for integer compare operations.
+ */
+class IntCompOp : public IntOp
+{
+ protected:
+
+ bool l;
+ uint8_t bf;
+
+ /// Constructor
+ IntCompOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntOp(mnem, _machInst, __opClass),
+ l(machInst.l),
+ bf(machInst.bf)
+ {
+ }
+};
+
+
+/**
+ * Class for integer immediate compare operations.
+ */
+class IntImmCompOp : public IntCompOp
+{
+ protected:
+
+ int32_t si;
+
+ /// Constructor
+ IntImmCompOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+ : IntCompOp(mnem, _machInst, __opClass),
+ si(sext<16>(machInst.si))
+ {
+ }
+};
+
+
+/**
+ * Class for integer immediate compare logical operations.
+ */
+class IntImmCompLogicOp : public IntCompOp
+{
+ protected:
+
+ uint32_t ui;
+
+ /// Constructor
+ IntImmCompLogicOp(const char *mnem, MachInst _machInst, OpClass
__opClass)
+ : IntCompOp(mnem, _machInst, __opClass),
+ ui(machInst.ui)
+ {
+ }
+};
+
+
+/**
* Class for integer operations with a shift.
*/
class IntShiftOp : public IntOp
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 3aa973f..221365e 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -73,19 +73,13 @@
}}, true);
}
- format IntImmOp {
- 10: cmpli({{
- Xer xer = XER;
- uint32_t cr = makeCRFieldUnsigned(Ra_uw, ui, xer.so);
- CR = insertCRField(CR, BF, cr);
- }});
+ 10: IntImmCompLogicOp::cmpli({{
+ cr = makeCRFieldUnsigned(Ra_uw, ui, xer.so);
+ }});
- 11: cmpi({{
- Xer xer = XER;
- uint32_t cr = makeCRFieldSigned(Ra_sw, si, xer.so);
- CR = insertCRField(CR, BF, cr);
- }});
- }
+ 11: IntImmCompOp::cmpi({{
+ cr = makeCRFieldSigned(Ra_sw, si, xer.so);
+ }});
format IntImmArithOp {
12: addic({{
@@ -223,10 +217,8 @@
// nested default cases.
31: decode X_XO {
- 0: IntOp::cmp({{
- Xer xer = XER;
- uint32_t cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
- CR = insertCRField(CR, BF, cr);
+ 0: IntCompOp::cmp({{
+ cr = makeCRFieldSigned(Ra_sw, Rb_sw, xer.so);
}});
format LoadIndexOp {
@@ -252,10 +244,8 @@
28: and({{ Ra = Rs & Rb; }});
}
- 32: IntOp::cmpl({{
- Xer xer = XER;
- uint32_t cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
- CR = insertCRField(CR, BF, cr);
+ 32: IntCompOp::cmpl({{
+ cr = makeCRFieldUnsigned(Ra_uw, Rb_uw, xer.so);
}});
52: LoadIndexOp::lbarx({{
diff --git a/src/arch/power/isa/formats/integer.isa
b/src/arch/power/isa/formats/integer.isa
index 924198d..04fe79e 100644
--- a/src/arch/power/isa/formats/integer.isa
+++ b/src/arch/power/isa/formats/integer.isa
@@ -179,6 +179,57 @@
}};
+// Integer compare instructions.
+def format IntCompOp(code, inst_flags = []) {{
+
+ # Add code to setup variables
+ code = 'GEM5_VAR_USED uint32_t cr = 0;\n' + code
+ code += 'CR = insertCRField(CR, bf, cr);\n'
+
+ # Add code to access XER
+ code = readXERCode + code
+
+ # Generate the class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntCompOp', code, inst_flags, BasicDecode,
+ BasicConstructor)
+}};
+
+
+// Integer immediate compare instructions.
+def format IntImmCompOp(code, inst_flags = []) {{
+
+ # Add code to setup variables
+ code = 'GEM5_VAR_USED uint32_t cr = 0;\n' + code
+ code += 'CR = insertCRField(CR, bf, cr);\n'
+
+ # Add code to access XER
+ code = readXERCode + code
+
+ # Generate the class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntImmCompOp', code, inst_flags, BasicDecode,
+ BasicConstructor)
+}};
+
+
+// Integer immediate compare logical instructions.
+def format IntImmCompLogicOp(code, inst_flags = []) {{
+
+ # Add code to setup variables
+ code = 'GEM5_VAR_USED uint32_t cr = 0;\n' + code
+ code += 'CR = insertCRField(CR, bf, cr);\n'
+
+ # Add code to access XER
+ code = readXERCode + code
+
+ # Generate the class
+ (header_output, decoder_output, decode_block, exec_output) = \
+ GenAluOp(name, Name, 'IntImmCompLogicOp', code, inst_flags,
+ BasicDecode, BasicConstructor)
+}};
+
+
// Integer instructions that perform logic operations. The result is
// always written into Ra. All instructions have 2 versions depending on
// whether the Rc bit is set to compute the CR0 code. This is determined
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic6feb803b3a22225d90b8712babd42889b67969d
Gerrit-Change-Number: 40912
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Sandipan Das <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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