Hey ARM folks. Could someone please explain to me what the deal is with the vector registers and renaming modes? What is fundamentally going on there? My best guess is that the granularity that the registers are being renamed at changes between the modes, or in other words you index by and rename by entire registers in one mode, and in the other mode you index by and rename by just the "elements" within the registers?
Are the "elements" or "lanes" or whatever in the registers fixed in size? How are these registers organized structurally? I've tried reading the code for the structures behind them before, but I get lost in the difference between vector registers, vector register containers, elements, lanes, predicates, etc etc. I need a big picture of what all these parts are and how they interrelate. Also, it's not a *great* sign if in order to understand this supposedly generic mechanism I need to have knowledge of how vector registers are implemented in such-and-such extension which is part of ARM. That's not particularly generic... Although hopefully it could be reworked to be! Gabe
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