Hi Gabe > -----Original Message----- > From: Gabe Black via gem5-dev <[email protected]> > Sent: 23 February 2021 08:54 > To: gem5 Developer List <[email protected]> > Cc: Gabe Black <[email protected]> > Subject: [gem5-dev] vector register indexing modes and renaming? > > Hey ARM folks. Could someone please explain to me what the deal is with the > vector registers and renaming modes? What is fundamentally going on there? > My best guess is that the granularity that the registers are being renamed at > changes between the modes, or in other words you index by and rename by > entire registers in one mode, and in the other mode you index by and rename > by just the "elements" within the registers?
Yes that is correct, let me know if you need further info on this > > Are the "elements" or "lanes" or whatever in the registers fixed in size? How > are these registers organized structurally? I've tried reading the code for > the > structures behind them before, but I get lost in the difference between vector > registers, vector register containers, elements, lanes, predicates, etc etc. > I need > a big picture of what all these parts are and how they interrelate. > > Also, it's not a *great* sign if in order to understand this supposedly > generic > mechanism I need to have knowledge of how vector registers are implemented > in such-and-such extension which is part of ARM. That's not particularly > generic... Although hopefully it could be reworked to be! > > Gabe While I believe there is room for improvement for the current vector data type in gem5, that is not an Arm only implementation. All the names you mentioned are standard terminology in computer architecture / SIMD implementations. (except for "containers", which is simply a made up name in gem5 to describe the vector storage). For example, predicates are a way to do element-wise masking (predicating) in vector operations. Those are called opmask registers in x86 AVX-512 [1] and predicate registers in the RISCV vector proposal [2] (I don't know what's the status of it though) and in Arm SVE Kind Regards Giacomo [1]: https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf [2]: https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list -- [email protected] To unsubscribe send an email to [email protected] %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
