Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/46622 )
Change subject: cpu: Do not generate a DTB node in the CheckerCPU
......................................................................
cpu: Do not generate a DTB node in the CheckerCPU
The CheckerCPU is not a real CPU and shouldn't generate a DTB
node. This is why we are skipping the BaseCPU implementation
and we are calling the base SimObject one.
Signed-off-by: Giacomo Travaglini <[email protected]>
Change-Id: I42326be9d4c440846fdf8d43bf809ad4d50f61d9
---
M src/cpu/CheckerCPU.py
1 file changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index c39bc13..d08d86a 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -27,6 +27,7 @@
from m5.params import *
from m5.objects.BaseCPU import BaseCPU
+from m5.SimObject import SimObject
class CheckerCPU(BaseCPU):
type = 'CheckerCPU'
@@ -37,3 +38,9 @@
"Update the checker with the main CPU's state on an error")
warnOnlyOnLoadError = Param.Bool(True,
"If a load result is incorrect, only print a warning and do not
exit")
+
+ def generateDeviceTree(self, state):
+ # The CheckerCPU is not a real CPU and shouldn't generate a DTB
+ # node. This is why we are skipping the BaseCPU implementation
+ # and we are calling the base SimObject one.
+ return SimObject.generateDeviceTree(self, state)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I42326be9d4c440846fdf8d43bf809ad4d50f61d9
Gerrit-Change-Number: 46622
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
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