Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/45782 )
Change subject: arch-arm: Remove the TLB::flush overload for TLBI IPA
......................................................................
arch-arm: Remove the TLB::flush overload for TLBI IPA
This will be handled by the MMU
Change-Id: I2cc2cae2a742f3c795867b7b85826e482cacc888
Signed-off-by: Giacomo Travaglini <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/45782
Tested-by: kokoro <[email protected]>
Reviewed-by: Andreas Sandberg <[email protected]>
Maintainer: Andreas Sandberg <[email protected]>
---
M src/arch/arm/tlb.cc
M src/arch/arm/tlb.hh
M src/arch/arm/tlbi_op.cc
M src/arch/arm/tlbi_op.hh
4 files changed, 8 insertions(+), 18 deletions(-)
Approvals:
Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index d759819..c8174b4 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -452,15 +452,6 @@
}
void
-TLB::flush(const TLBIIPA &tlbi_op)
-{
- assert(!isStage2);
-
- // Note, TLBIIPA::makeStage2 will generare a TLBIMVAA
- stage2Tlb->flush(tlbi_op.makeStage2());
-}
-
-void
TLB::drainResume()
{
// We might have unserialized something or switched CPUs, so make
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 3d96446..b59fd67 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -66,7 +66,6 @@
class TLBIMVA;
class TLBIASID;
class TLBIMVAA;
-class TLBIIPA;
class TlbTestInterface
{
@@ -294,12 +293,6 @@
*/
void flush(const TLBIMVAA &tlbi_op);
- /**
- * Invalidate all entries in the stage 2 TLB that match the given ipa
- * and the current VMID
- */
- void flush(const TLBIIPA &tlbi_op);
-
Fault trickBoxCheck(const RequestPtr &req, Mode mode,
TlbEntry::DomainType domain);
diff --git a/src/arch/arm/tlbi_op.cc b/src/arch/arm/tlbi_op.cc
index 5bcc009..d918454 100644
--- a/src/arch/arm/tlbi_op.cc
+++ b/src/arch/arm/tlbi_op.cc
@@ -182,11 +182,11 @@
void
TLBIIPA::operator()(ThreadContext* tc)
{
- getMMUPtr(tc)->flush(*this);
+ getMMUPtr(tc)->flushStage2(makeStage2());
CheckerCPU *checker = tc->getCheckerCpuPtr();
if (checker) {
- getMMUPtr(checker)->flush(*this);
+ getMMUPtr(checker)->flushStage2(makeStage2());
}
}
diff --git a/src/arch/arm/tlbi_op.hh b/src/arch/arm/tlbi_op.hh
index 924aabd..e2f3eee 100644
--- a/src/arch/arm/tlbi_op.hh
+++ b/src/arch/arm/tlbi_op.hh
@@ -343,6 +343,12 @@
void operator()(ThreadContext* tc) override;
+ bool
+ stage1Flush() const override
+ {
+ return false;
+ }
+
/** TLBIIPA is basically a TLBIMVAA for stage2 TLBs */
TLBIMVAA
makeStage2() const
5 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I2cc2cae2a742f3c795867b7b85826e482cacc888
Gerrit-Change-Number: 45782
Gerrit-PatchSet: 7
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Andreas Sandberg <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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