Sandipan Das has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40919 )
Change subject: arch-power: Add sign-extend instructions
......................................................................
arch-power: Add sign-extend instructions
This adds the following instructions.
* Extend Sign Word (extsw[.])
Change-Id: Ia15fc69de665399f1c8d52ca00d2f7670d553b48
Signed-off-by: Sandipan Das <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40919
Reviewed-by: Boris Shingarov <[email protected]>
Maintainer: Boris Shingarov <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/power/insts/integer.cc
M src/arch/power/isa/decoder.isa
2 files changed, 2 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/insts/integer.cc
b/src/arch/power/insts/integer.cc
index 43ef210..d7c8ed4 100644
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -286,6 +286,7 @@
printSecondSrc = false;
} else if (myMnemonic == "extsb" ||
myMnemonic == "extsh" ||
+ myMnemonic == "extsw" ||
myMnemonic == "cntlzw") {
printSecondSrc = false;
}
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 40311fa..0ec249e 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -579,6 +579,7 @@
}
983: StoreIndexOp::stfiwx({{ Mem = Fs_uw; }});
+ 986: IntLogicOp::extsw({{ Ra = sext<32>(Rs); }}, true);
// These instructions are of XO form with bit 21 as the OE bit.
default: decode XO_XO {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia15fc69de665399f1c8d52ca00d2f7670d553b48
Gerrit-Change-Number: 40919
Gerrit-PatchSet: 8
Gerrit-Owner: Sandipan Das <[email protected]>
Gerrit-Reviewer: Boris Shingarov <[email protected]>
Gerrit-Reviewer: Sandipan Das <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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