Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40935 )
Change subject: arch-power: Fix move condition field instructions
......................................................................
arch-power: Fix move condition field instructions
This introduces the S field for X form instructions which
is used to specify signed versus unsigned comparison. The
Power ISA does not specify a formal name for the third
1-bit opcode field required for decoding XFX form move to
and from CR field instructions, the S field can be used
to achieve the same as it has the same span and position.
This fixes the following instructions.
* Move To Condition Register Fields (mtcrf)
* Move From Condition Register (mfcr)
Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40935
Reviewed-by: Boris Shingarov <shinga...@labware.com>
Maintainer: Boris Shingarov <shinga...@labware.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/power/isa/bitfields.isa
M src/arch/power/isa/decoder.isa
2 files changed, 14 insertions(+), 9 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/bitfields.isa
b/src/arch/power/isa/bitfields.isa
index 3bfea53..276242e 100644
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -73,6 +73,7 @@
// FXM field for mtcrf instruction
def bitfield FXM <19:12>;
+def bitfield S <20>;
// Branch fields
def bitfield BO <25:21>;
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 6c73b28..4307b25 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -978,17 +978,21 @@
default: decode XFX_XO {
format IntOp {
- 19: mfcr({{ Rt = CR; }});
+ 19: decode S {
+ 0: mfcr({{ Rt = CR; }});
+ }
- 144: mtcrf({{
- uint32_t mask = 0;
- for (int i = 0; i < 8; ++i) {
- if (((FXM >> i) & 0x1) == 0x1) {
- mask |= 0xf << (4 * i);
+ 144: decode S {
+ 0: mtcrf({{
+ uint32_t mask = 0;
+ for (int i = 0; i < 8; ++i) {
+ if (bits(FXM, i)) {
+ mask |= 0xf << (4 * i);
+ }
}
- }
- CR = (Rs & mask) | (CR & ~mask);
- }});
+ CR = (Rs & mask) | (CR & ~mask);
+ }});
+ }
339: decode SPR {
0x20: mfxer({{ Rt = XER; }});
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8d291f707cd063781f0497f7226bebfc47bd9e63
Gerrit-Change-Number: 40935
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-Reviewer: Boris Shingarov <shinga...@labware.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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