Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40936 )
Change subject: arch-power: Add move condition field instructions
......................................................................
arch-power: Add move condition field instructions
This adds the following instructions.
* Move to CR from XER Extended (mcrxrx)
* Move To One Condition Register Field (mtocrf)
* Move From One Condition Register Field (mfocrf)
Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Signed-off-by: Sandipan Das <sandi...@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40936
Reviewed-by: Boris Shingarov <shinga...@labware.com>
Maintainer: Boris Shingarov <shinga...@labware.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/power/isa/decoder.isa
1 file changed, 24 insertions(+), 0 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 4307b25..d752630 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -638,6 +638,14 @@
567: LoadIndexUpdateOp::lfsux({{ Ft_sf = Mem_sf; }});
570: IntLogicOp::cnttzd({{ Ra = findTrailingZeros(Rs); }}, true);
+
+ 576: IntOp::mcrxrx({{
+ uint8_t res;
+ Xer xer = XER;
+ res = (xer.ov << 3) | (xer.ov32 << 2) | (xer.ca << 1) |
xer.ca32;
+ CR = insertCRField(CR, BF, res);
+ }});
+
598: MiscOp::sync({{ }}, [ IsReadBarrier, IsWriteBarrier ]);
599: LoadIndexOp::lfdx({{ Ft = Mem_df; }});
631: LoadIndexUpdateOp::lfdux({{ Ft = Mem_df; }});
@@ -980,6 +988,14 @@
format IntOp {
19: decode S {
0: mfcr({{ Rt = CR; }});
+
+ 1: mfocrf({{
+ int count = popCount(FXM);
+ uint64_t mask = 0xf << (4 *
findMsbSet(FXM));
+ if (count == 1) {
+ Rt = CR & mask;
+ }
+ }});
}
144: decode S {
@@ -992,6 +1008,14 @@
}
CR = (Rs & mask) | (CR & ~mask);
}});
+
+ 1: mtocrf({{
+ int count = popCount(FXM);
+ uint32_t mask = 0xf << (4 *
findMsbSet(FXM));
+ if (count == 1) {
+ CR = (Rs & mask) | (CR & ~mask);
+ }
+ }});
}
339: decode SPR {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5014160d77b1b759c1cb8cba34e6dd20eb2b5205
Gerrit-Change-Number: 40936
Gerrit-PatchSet: 10
Gerrit-Owner: Sandipan Das <sandi...@linux.ibm.com>
Gerrit-Reviewer: Boris Shingarov <shinga...@labware.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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