Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49363 )
Change subject: configs: Update component API for I/O
......................................................................
configs: Update component API for I/O
This change adds a check for coherent I/O ports from the board. This
change allows us to move some of the cache hierarchy specific code out
of the board and into the cache hierarchies.
Change-Id: Ib8144b6d8579ee71e86e4823d2cd396f9cb254ba
Signed-off-by: Jason Lowe-Power <[email protected]>
---
M components_library/boards/abstract_board.py
M components_library/boards/simple_board.py
M components_library/boards/test_board.py
M components_library/boards/x86_board.py
M components_library/cachehierarchies/classic/no_cache.py
M
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
6 files changed, 75 insertions(+), 20 deletions(-)
diff --git a/components_library/boards/abstract_board.py
b/components_library/boards/abstract_board.py
index 3eae0e0..c83668b 100644
--- a/components_library/boards/abstract_board.py
+++ b/components_library/boards/abstract_board.py
@@ -145,6 +145,24 @@
raise NotImplementedError
@abstractmethod
+ def has_coherent_io(self) -> bool:
+ """Determine whether the board needs coherent I/O
+
+ :returns: True if the board needs coherent I/O, false otherwise
+ """
+ raise NotImplementedError
+
+ @abstractmethod
+ def get_mem_side_coherent_io_port(self):
+ """Get the memory-side coherent I/O port.
+ This abstract method must be implemented if has_coherent_io is
true.
+
+ This returns a *port* (not a bus) that should be connected to a
+ CPU-side port for which coherent I/O (DMA) is issued.
+ """
+ raise NotImplementedError
+
+ @abstractmethod
def get_clock_domain(self) -> ClockDomain:
"""Get the clock domain.
diff --git a/components_library/boards/simple_board.py
b/components_library/boards/simple_board.py
index fdba342..8ecaefc 100644
--- a/components_library/boards/simple_board.py
+++ b/components_library/boards/simple_board.py
@@ -126,6 +126,17 @@
)
@overrides(AbstractBoard)
+ def has_coherent_io(self) -> bool:
+ return False
+
+ @overrides(AbstractBoard)
+ def get_mem_side_coherent_io_port(self) -> Port:
+ raise NotImplementedError(
+ "SimpleBoard does not have any I/O ports. Use has_coherent_io
to "
+ "check this."
+ )
+
+ @overrides(AbstractBoard)
def setup_memory_ranges(self) -> None:
memory = self.get_memory()
diff --git a/components_library/boards/test_board.py
b/components_library/boards/test_board.py
index 567a4ad..b64e514 100644
--- a/components_library/boards/test_board.py
+++ b/components_library/boards/test_board.py
@@ -106,6 +106,17 @@
)
@overrides(AbstractBoard)
+ def has_coherent_io(self) -> bool:
+ return False
+
+ @overrides(AbstractBoard)
+ def get_mem_side_coherent_io_port(self):
+ raise NotImplementedError(
+ "SimpleBoard does not have any I/O ports. Use has_coherent_io
to "
+ "check this."
+ )
+
+ @overrides(AbstractBoard)
def set_mem_mode(self, mem_mode: MemMode) -> None:
self.mem_mode = mem_mode_to_string(mem_mode=mem_mode)
diff --git a/components_library/boards/x86_board.py
b/components_library/boards/x86_board.py
index 11a223f..dd9ad13 100644
--- a/components_library/boards/x86_board.py
+++ b/components_library/boards/x86_board.py
@@ -99,6 +99,9 @@
self.workload = X86FsLinux()
+ # North Bridge
+ self.iobus = IOXBar()
+
def _setup_io_devices(self):
""" Sets up the x86 IO devices.
@@ -112,9 +115,6 @@
interrupts_address_space_base = 0xA000000000000000
APIC_range_size = 1 << 12
- # North Bridge
- self.iobus = IOXBar()
-
# Setup memory system specific settings.
if self.get_cache_hierarchy().is_ruby():
self.pc.attachIO(self.get_io_bus(),
[self.pc.south_bridge.ide.dma])
@@ -154,22 +154,6 @@
]
self.pc.attachIO(self.get_io_bus())
- self.iocache = Cache(
- assoc=8,
- tag_latency=50,
- data_latency=50,
- response_latency=50,
- mshrs=20,
- size="1kB",
- tgts_per_mshr=12,
- addr_ranges=self.mem_ranges,
- )
-
- self.iocache.cpu_side = self.get_io_bus().mem_side_ports
- self.iocache.mem_side = (
- self.get_cache_hierarchy().get_cpu_side_port()
- )
-
# Add in a Bios information structure.
self.workload.smbios_table.structures =
[X86SMBiosBiosInformation()]
@@ -361,6 +345,14 @@
return [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports]
@overrides(AbstractBoard)
+ def has_coherent_io(self) -> bool:
+ return True
+
+ @overrides(AbstractBoard)
+ def get_mem_side_coherent_io_port(self) -> Port:
+ return self.iobus.mem_side_ports
+
+ @overrides(AbstractBoard)
def setup_memory_ranges(self):
memory = self.get_memory()
diff --git a/components_library/cachehierarchies/classic/no_cache.py
b/components_library/cachehierarchies/classic/no_cache.py
index 44933bf..106b74f 100644
--- a/components_library/cachehierarchies/classic/no_cache.py
+++ b/components_library/cachehierarchies/classic/no_cache.py
@@ -33,7 +33,7 @@
from ...isas import ISA
from ...runtime import get_runtime_isa
-from m5.objects import BaseXBar, SystemXBar, BadAddr, Port
+from m5.objects import Bridge, BaseXBar, SystemXBar, BadAddr, Port
from typing import Optional
@@ -101,6 +101,9 @@
@overrides(AbstractCacheHierarchy)
def incorporate_cache(self, board: AbstractBoard) -> None:
+ if board.has_coherent_io():
+ self._setup_coherent_io_bridge(board)
+
for core in board.get_processor().get_cores():
core.connect_icache(self.membus.cpu_side_ports)
@@ -121,3 +124,9 @@
for cntr in board.get_memory().get_memory_controllers():
cntr.port = self.membus.mem_side_ports
+
+ def _setup_coherent_io_bridge(self, board: AbstractBoard) -> None:
+ """Create a bridge from I/O back to membus"""
+ self.iobridge = Bridge(delay="10ns", ranges=board.mem_ranges)
+ self.iobridge.mem_side_port = self.membus.cpu_side_ports
+ self.iobridge.cpu_side_port = board.get_mem_side_coherent_io_port()
diff --git
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index 012743e..a2a10fc 100644
---
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -159,3 +159,17 @@
cpu.connect_interrupt(int_req_port, int_resp_port)
else:
cpu.connect_interrupt()
+ def _setup_io_cache(self, board: AbstractBoard) -> None:
+ """Create a cache for coherent I/O connections"""
+ self.iocache = Cache(
+ assoc=8,
+ tag_latency=50,
+ data_latency=50,
+ response_latency=50,
+ mshrs=20,
+ size="1kB",
+ tgts_per_mshr=12,
+ addr_ranges=board.mem_ranges,
+ )
+ self.iocache.mem_side = self.membus.cpu_side_ports
+ self.iocache.cpu_side = board.get_mem_side_coherent_io_port()
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib8144b6d8579ee71e86e4823d2cd396f9cb254ba
Gerrit-Change-Number: 49363
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <[email protected]>
Gerrit-MessageType: newchange
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