Jason Lowe-Power has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49344 )
Change subject: configs: Create interrupts for ISAs other than x86
......................................................................
configs: Create interrupts for ISAs other than x86
All CPUs need to have `createInterrupts()` called. Add a switch to check
for that in the caches and make the ports optional parameters.
Change-Id: I38310c57a68ef18fbe1c28844dcda515eca3170e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49344
Maintainer: Bobby R. Bruce <[email protected]>
Tested-by: kokoro <[email protected]>
Reviewed-by: Bobby R. Bruce <[email protected]>
---
M components_library/cachehierarchies/classic/no_cache.py
M
components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
M components_library/processors/abstract_core.py
M components_library/processors/simple_core.py
4 files changed, 15 insertions(+), 2 deletions(-)
Approvals:
Bobby R. Bruce: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/components_library/cachehierarchies/classic/no_cache.py
b/components_library/cachehierarchies/classic/no_cache.py
index 9b8a49c..44933bf 100644
--- a/components_library/cachehierarchies/classic/no_cache.py
+++ b/components_library/cachehierarchies/classic/no_cache.py
@@ -113,6 +113,8 @@
int_req_port = self.membus.mem_side_ports
int_resp_port = self.membus.cpu_side_ports
core.connect_interrupt(int_req_port, int_resp_port)
+ else:
+ core.connect_interrupt()
# Set up the system port for functional access from the simulator.
board.connect_system_port(self.membus.cpu_side_ports)
diff --git
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
index bf357c5..012743e 100644
---
a/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
+++
b/components_library/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
@@ -157,3 +157,5 @@
int_req_port = self.membus.mem_side_ports
int_resp_port = self.membus.cpu_side_ports
cpu.connect_interrupt(int_req_port, int_resp_port)
+ else:
+ cpu.connect_interrupt()
diff --git a/components_library/processors/abstract_core.py
b/components_library/processors/abstract_core.py
index 68f8db1..35225c1 100644
--- a/components_library/processors/abstract_core.py
+++ b/components_library/processors/abstract_core.py
@@ -25,6 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from abc import ABCMeta, abstractmethod
+from typing import Optional
from .cpu_types import CPUTypes
from m5.objects import Port, SubSystem
@@ -81,6 +82,12 @@
@abstractmethod
def connect_interrupt(
- self, interrupt_requestor: Port, interrupt_responce: Port
+ self, interrupt_requestor: Optional[Port] = None,
+ interrupt_responce: Optional[Port] = None
) -> None:
+ """ Connect the core interrupts to the interrupt controller
+
+ This function is usually called from the cache hierarchy since the
+ optional ports can be implemented as cache ports.
+ """
raise NotImplementedError
diff --git a/components_library/processors/simple_core.py
b/components_library/processors/simple_core.py
index 4f8a4a6..c093856 100644
--- a/components_library/processors/simple_core.py
+++ b/components_library/processors/simple_core.py
@@ -24,6 +24,7 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+from typing import Optional
from components_library.runtime import get_runtime_isa
from components_library.processors.abstract_core import AbstractCore
@@ -83,7 +84,8 @@
@overrides(AbstractCore)
def connect_interrupt(
- self, interrupt_requestor: Port, interrupt_responce: Port
+ self, interrupt_requestor: Optional[Port] = None,
+ interrupt_responce: Optional[Port] = None
) -> None:
# TODO: This model assumes that we will only create an interrupt
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I38310c57a68ef18fbe1c28844dcda515eca3170e
Gerrit-Change-Number: 49344
Gerrit-PatchSet: 2
Gerrit-Owner: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Bobby R. Bruce <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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