Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49727 )
Change subject: arch: Create a new operand desc type which takes a class as
a parameter.
......................................................................
arch: Create a new operand desc type which takes a class as a parameter.
This will be the basis for an operand type which can override its
register class if needed.
Change-Id: I415b70d6d655efc9f6b32102a8482e2cca2fa613
---
M src/arch/isa_parser/operand_types.py
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index b71515d..331fed3 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -278,33 +278,42 @@
traceData->setData(final_val);
}}'''
+class RegOperandDesc(OperandDesc):
+ def __init__(self, reg_class, *args, **kwargs):
+ super(RegOperandDesc, self).__init__(*args, **kwargs)
+ self.attrs['reg_class'] = reg_class
+
class IntRegOperand(RegOperand):
reg_class = 'IntRegClass'
-class IntRegOperandDesc(OperandDesc):
+class IntRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
- super(IntRegOperandDesc, self).__init__('IntReg', *args, **kwargs)
+ super(IntRegOperandDesc, self).__init__(
+ 'IntRegClass', 'Reg', *args, **kwargs)
class FloatRegOperand(RegOperand):
reg_class = 'FloatRegClass'
-class FloatRegOperandDesc(OperandDesc):
+class FloatRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
- super(FloatRegOperandDesc, self).__init__('FloatReg', *args,
**kwargs)
+ super(FloatRegOperandDesc, self).__init__(
+ 'FloatRegClass', 'Reg', *args, **kwargs)
class CCRegOperand(RegOperand):
reg_class = 'CCRegClass'
-class CCRegOperandDesc(OperandDesc):
+class CCRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
- super(CCRegOperandDesc, self).__init__('CCReg', *args, **kwargs)
+ super(CCRegOperandDesc, self).__init__(
+ 'CCRegClass', 'Reg', *args, **kwargs)
class VecElemOperand(RegOperand):
reg_class = 'VecElemClass'
-class VecElemOperandDesc(OperandDesc):
+class VecElemOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
- super(VecElemOperandDesc, self).__init__('VecElem', *args,
**kwargs)
+ super(VecElemOperandDesc, self).__init__(
+ 'VecElemClass', 'Reg', *args, **kwargs)
class VecRegOperand(BaseRegOperand):
reg_class = 'VecRegClass'
@@ -434,9 +443,10 @@
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
-class VecRegOperandDesc(OperandDesc):
+class VecRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
- super(VecRegOperandDesc, self).__init__('VecReg', *args, **kwargs)
+ super(VecRegOperandDesc, self).__init__(
+ 'VecRegClass', 'VecReg', *args, **kwargs)
class VecPredRegOperand(BaseRegOperand):
reg_class = 'VecPredRegClass'
@@ -499,10 +509,10 @@
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
-class VecPredRegOperandDesc(OperandDesc):
+class VecPredRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(VecPredRegOperandDesc, self).__init__(
- 'VecPredReg', *args, **kwargs)
+ 'VecPredRegClass', 'VecPredReg', *args, **kwargs)
class ControlRegOperand(Operand):
reg_class = 'MiscRegClass'
@@ -558,10 +568,10 @@
return wb
-class ControlRegOperandDesc(OperandDesc):
+class ControlRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(ControlRegOperandDesc, self).__init__(
- 'ControlReg', *args, **kwargs)
+ 'MiscRegClass', 'ControlReg', *args, **kwargs)
class MemOperand(Operand):
def isMem(self):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I415b70d6d655efc9f6b32102a8482e2cca2fa613
Gerrit-Change-Number: 49727
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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