Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/49727 )

 (

59 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one. )Change subject: arch: Create a new operand desc type which takes a class as a parameter.
......................................................................

arch: Create a new operand desc type which takes a class as a parameter.

This will be the basis for an operand type which can override its
register class if needed.

Change-Id: I415b70d6d655efc9f6b32102a8482e2cca2fa613
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49727
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/isa_parser/operand_types.py
1 file changed, 35 insertions(+), 14 deletions(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/arch/isa_parser/operand_types.py b/src/arch/isa_parser/operand_types.py
index 262659a..a6eb976 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -278,33 +278,38 @@
                 traceData->setData(final_val);
         }}'''

+class RegOperandDesc(OperandDesc):
+    def __init__(self, reg_class, *args, **kwargs):
+        super().__init__(*args, **kwargs)
+        self.attrs['reg_class'] = reg_class
+
 class IntRegOperand(RegValOperand):
     reg_class = 'IntRegClass'

-class IntRegOperandDesc(OperandDesc):
+class IntRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
-        super().__init__('IntReg', *args, **kwargs)
+        super().__init__('IntRegClass', 'RegVal', *args, **kwargs)

 class FloatRegOperand(RegValOperand):
     reg_class = 'FloatRegClass'

-class FloatRegOperandDesc(OperandDesc):
+class FloatRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
-        super().__init__('FloatReg', *args, **kwargs)
+        super().__init__('FloatRegClass', 'RegVal', *args, **kwargs)

 class CCRegOperand(RegValOperand):
     reg_class = 'CCRegClass'

-class CCRegOperandDesc(OperandDesc):
+class CCRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
-        super().__init__('CCReg', *args, **kwargs)
+        super().__init__('CCRegClass', 'RegVal', *args, **kwargs)

 class VecElemOperand(RegValOperand):
     reg_class = 'VecElemClass'

-class VecElemOperandDesc(OperandDesc):
+class VecElemOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
-        super().__init__('VecElem', *args, **kwargs)
+        super().__init__('VecElemClass', 'RegVal', *args, **kwargs)

 class VecRegOperand(RegOperand):
     reg_class = 'VecRegClass'
@@ -434,9 +439,9 @@
         if self.is_dest:
             self.op_rd = self.makeReadW(predWrite) + self.op_rd

-class VecRegOperandDesc(OperandDesc):
+class VecRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
-        super().__init__('VecReg', *args, **kwargs)
+        super().__init__('VecRegClass', 'VecReg', *args, **kwargs)

 class VecPredRegOperand(RegOperand):
     reg_class = 'VecPredRegClass'
@@ -499,9 +504,9 @@
         if self.is_dest:
             self.op_rd = self.makeReadW(predWrite) + self.op_rd

-class VecPredRegOperandDesc(OperandDesc):
+class VecPredRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
-        super().__init__('VecPredReg', *args, **kwargs)
+        super().__init__('VecPredRegClass', 'VecPredReg', *args, **kwargs)

 class ControlRegOperand(Operand):
     reg_class = 'MiscRegClass'
@@ -557,9 +562,9 @@

         return wb

-class ControlRegOperandDesc(OperandDesc):
+class ControlRegOperandDesc(RegOperandDesc):
     def __init__(self, *args, **kwargs):
-        super().__init__('ControlReg', *args, **kwargs)
+        super().__init__('MiscRegClass', 'ControlReg', *args, **kwargs)

 class MemOperand(Operand):
     def isMem(self):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I415b70d6d655efc9f6b32102a8482e2cca2fa613
Gerrit-Change-Number: 49727
Gerrit-PatchSet: 62
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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