Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49731 )
Change subject: arch-riscv: Use the OperandDesc classes in the ISA
description.
......................................................................
arch-riscv: Use the OperandDesc classes in the ISA description.
Change-Id: I1316dcc628bb634549a626ca244a62aa9f76638c
---
M src/arch/riscv/isa/operands.isa
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/src/arch/riscv/isa/operands.isa
b/src/arch/riscv/isa/operands.isa
index 78cd5f9..8d0a1a2 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -43,38 +43,38 @@
def operands {{
#General Purpose Integer Reg Operands
- 'Rd': ('IntReg', 'ud', 'RD', 'IsInteger', 1),
- 'Rs1': ('IntReg', 'ud', 'RS1', 'IsInteger', 2),
- 'Rs2': ('IntReg', 'ud', 'RS2', 'IsInteger', 3),
- 'Rt': ('IntReg', 'ud', 'AMOTempReg', 'IsInteger', 4),
- 'Rc1': ('IntReg', 'ud', 'RC1', 'IsInteger', 2),
- 'Rc2': ('IntReg', 'ud', 'RC2', 'IsInteger', 3),
- 'Rp1': ('IntReg', 'ud', 'RP1 + 8', 'IsInteger', 2),
- 'Rp2': ('IntReg', 'ud', 'RP2 + 8', 'IsInteger', 3),
- 'ra': ('IntReg', 'ud', 'ReturnAddrReg', 'IsInteger', 1),
- 'sp': ('IntReg', 'ud', 'StackPointerReg', 'IsInteger', 2),
+ 'Rd': IntRegOp('ud', 'RD', 'IsInteger', 1),
+ 'Rs1': IntRegOp('ud', 'RS1', 'IsInteger', 2),
+ 'Rs2': IntRegOp('ud', 'RS2', 'IsInteger', 3),
+ 'Rt': IntRegOp('ud', 'AMOTempReg', 'IsInteger', 4),
+ 'Rc1': IntRegOp('ud', 'RC1', 'IsInteger', 2),
+ 'Rc2': IntRegOp('ud', 'RC2', 'IsInteger', 3),
+ 'Rp1': IntRegOp('ud', 'RP1 + 8', 'IsInteger', 2),
+ 'Rp2': IntRegOp('ud', 'RP2 + 8', 'IsInteger', 3),
+ 'ra': IntRegOp('ud', 'ReturnAddrReg', 'IsInteger', 1),
+ 'sp': IntRegOp('ud', 'StackPointerReg', 'IsInteger', 2),
- 'a0': ('IntReg', 'ud', '10', 'IsInteger', 1),
+ 'a0': IntRegOp('ud', '10', 'IsInteger', 1),
- 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
- 'Fd_bits': ('FloatReg', 'ud', 'FD', 'IsFloating', 1),
- 'Fs1': ('FloatReg', 'df', 'FS1', 'IsFloating', 2),
- 'Fs1_bits': ('FloatReg', 'ud', 'FS1', 'IsFloating', 2),
- 'Fs2': ('FloatReg', 'df', 'FS2', 'IsFloating', 3),
- 'Fs2_bits': ('FloatReg', 'ud', 'FS2', 'IsFloating', 3),
- 'Fs3': ('FloatReg', 'df', 'FS3', 'IsFloating', 4),
- 'Fs3_bits': ('FloatReg', 'ud', 'FS3', 'IsFloating', 4),
- 'Fc1': ('FloatReg', 'df', 'FC1', 'IsFloating', 1),
- 'Fc1_bits': ('FloatReg', 'ud', 'FC1', 'IsFloating', 1),
- 'Fc2': ('FloatReg', 'df', 'FC2', 'IsFloatReg', 2),
- 'Fc2_bits': ('FloatReg', 'ud', 'FC2', 'IsFloating', 2),
- 'Fp2': ('FloatReg', 'df', 'FP2 + 8', 'IsFloating', 2),
- 'Fp2_bits': ('FloatReg', 'ud', 'FP2 + 8', 'IsFloating', 2),
+ 'Fd': FloatRegOp('df', 'FD', 'IsFloating', 1),
+ 'Fd_bits': FloatRegOp('ud', 'FD', 'IsFloating', 1),
+ 'Fs1': FloatRegOp('df', 'FS1', 'IsFloating', 2),
+ 'Fs1_bits': FloatRegOp('ud', 'FS1', 'IsFloating', 2),
+ 'Fs2': FloatRegOp('df', 'FS2', 'IsFloating', 3),
+ 'Fs2_bits': FloatRegOp('ud', 'FS2', 'IsFloating', 3),
+ 'Fs3': FloatRegOp('df', 'FS3', 'IsFloating', 4),
+ 'Fs3_bits': FloatRegOp('ud', 'FS3', 'IsFloating', 4),
+ 'Fc1': FloatRegOp('df', 'FC1', 'IsFloating', 1),
+ 'Fc1_bits': FloatRegOp('ud', 'FC1', 'IsFloating', 1),
+ 'Fc2': FloatRegOp('df', 'FC2', 'IsFloatReg', 2),
+ 'Fc2_bits': FloatRegOp('ud', 'FC2', 'IsFloating', 2),
+ 'Fp2': FloatRegOp('df', 'FP2 + 8', 'IsFloating', 2),
+ 'Fp2_bits': FloatRegOp('ud', 'FP2 + 8', 'IsFloating', 2),
#Memory Operand
- 'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 5),
+ 'Mem': MemOp('ud', None, (None, 'IsLoad', 'IsStore'), 5),
#Program Counter Operands
- 'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
- 'NPC': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 8),
+ 'PC': PCStateOp('ud', 'pc', (None, None, 'IsControl'), 7),
+ 'NPC': PCStateOp('ud', 'npc', (None, None, 'IsControl'), 8),
}};
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1316dcc628bb634549a626ca244a62aa9f76638c
Gerrit-Change-Number: 49731
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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