Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49774 )
Change subject: arch: Switch the generic register ABI over to use RegId.
......................................................................
arch: Switch the generic register ABI over to use RegId.
Change-Id: I4bbe884fe01fe14d7f18574f494a831dee2996d3
---
M src/arch/arm/reg_abi.cc
M src/arch/arm/reg_abi.hh
M src/arch/power/se_workload.cc
M src/arch/power/se_workload.hh
M src/arch/riscv/reg_abi.cc
M src/arch/riscv/reg_abi.hh
M src/arch/sparc/se_workload.cc
M src/arch/sparc/se_workload.hh
M src/arch/x86/linux/se_workload.cc
M src/arch/x86/linux/se_workload.hh
M src/sim/syscall_abi.hh
11 files changed, 30 insertions(+), 19 deletions(-)
diff --git a/src/arch/arm/reg_abi.cc b/src/arch/arm/reg_abi.cc
index 3422eb1..9c89b7d 100644
--- a/src/arch/arm/reg_abi.cc
+++ b/src/arch/arm/reg_abi.cc
@@ -26,6 +26,7 @@
*/
#include "arch/arm/reg_abi.hh"
+#include "arch/arm/regs/int.hh"
namespace gem5
{
@@ -33,8 +34,14 @@
namespace ArmISA
{
-const std::vector<int> RegABI32::ArgumentRegs = {0, 1, 2, 3, 4, 5, 6};
-const std::vector<int> RegABI64::ArgumentRegs = {0, 1, 2, 3, 4, 5, 6};
+const std::vector<RegId> RegABI32::ArgumentRegs = {
+ int_reg::R0, int_reg::R1, int_reg::R2, int_reg::R3,
+ int_reg::R4, int_reg::R5, int_reg::R6
+};
+const std::vector<RegId> RegABI64::ArgumentRegs = {
+ int_reg::X0, int_reg::X1, int_reg::X2, int_reg::X3,
+ int_reg::X4, int_reg::X5, int_reg::X6
+};
} // namespace ArmISA
} // namespace gem5
diff --git a/src/arch/arm/reg_abi.hh b/src/arch/arm/reg_abi.hh
index d8a0ffa..1d5272c 100644
--- a/src/arch/arm/reg_abi.hh
+++ b/src/arch/arm/reg_abi.hh
@@ -41,12 +41,12 @@
struct RegABI32 : public GenericSyscallABI32
{
- static const std::vector<int> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
struct RegABI64 : public GenericSyscallABI64
{
- static const std::vector<int> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
} // namespace ArmISA
diff --git a/src/arch/power/se_workload.cc b/src/arch/power/se_workload.cc
index 4177fc0..d9125c5 100644
--- a/src/arch/power/se_workload.cc
+++ b/src/arch/power/se_workload.cc
@@ -33,7 +33,7 @@
namespace PowerISA
{
-const std::vector<int> SEWorkload::SyscallABI::ArgumentRegs = {
+const std::vector<RegId> SEWorkload::SyscallABI::ArgumentRegs = {
ArgumentReg0,
ArgumentReg1,
ArgumentReg2,
diff --git a/src/arch/power/se_workload.hh b/src/arch/power/se_workload.hh
index 1923e4b..304defd 100644
--- a/src/arch/power/se_workload.hh
+++ b/src/arch/power/se_workload.hh
@@ -59,7 +59,7 @@
struct SyscallABI : public GenericSyscallABI64
{
- static const std::vector<int> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
};
diff --git a/src/arch/riscv/reg_abi.cc b/src/arch/riscv/reg_abi.cc
index 977bdff..b9827f7 100644
--- a/src/arch/riscv/reg_abi.cc
+++ b/src/arch/riscv/reg_abi.cc
@@ -26,6 +26,7 @@
*/
#include "arch/riscv/reg_abi.hh"
+#include "arch/riscv/regs/int.hh"
namespace gem5
{
@@ -33,7 +34,10 @@
namespace RiscvISA
{
-const std::vector<int> RegABI64::ArgumentRegs = {10, 11, 12, 13, 14, 15,
16};
+const std::vector<RegId> RegABI64::ArgumentRegs = {
+ int_reg::A0, int_reg::A1, int_reg::A2, int_reg::A3,
+ int_reg::A4, int_reg::A5, int_reg::A6
+};
} // namespace RiscvISA
} // namespace gem5
diff --git a/src/arch/riscv/reg_abi.hh b/src/arch/riscv/reg_abi.hh
index 91881e9..3419c31 100644
--- a/src/arch/riscv/reg_abi.hh
+++ b/src/arch/riscv/reg_abi.hh
@@ -41,7 +41,7 @@
//FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA.
struct RegABI64 : public GenericSyscallABI64
{
- static const std::vector<int> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
} // namespace RiscvISA
diff --git a/src/arch/sparc/se_workload.cc b/src/arch/sparc/se_workload.cc
index 9a846d4..5d2eac7 100644
--- a/src/arch/sparc/se_workload.cc
+++ b/src/arch/sparc/se_workload.cc
@@ -41,7 +41,7 @@
namespace SparcISA
{
-const std::vector<int> SEWorkload::BaseSyscallABI::ArgumentRegs = {
+const std::vector<RegId> SEWorkload::BaseSyscallABI::ArgumentRegs = {
int_reg::O0, int_reg::O1, int_reg::O2,
int_reg::O3, int_reg::O4, int_reg::O5
};
diff --git a/src/arch/sparc/se_workload.hh b/src/arch/sparc/se_workload.hh
index 11b3c4f..1b69835 100644
--- a/src/arch/sparc/se_workload.hh
+++ b/src/arch/sparc/se_workload.hh
@@ -63,7 +63,7 @@
struct BaseSyscallABI
{
- static const std::vector<int> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
struct SyscallABI32 : public GenericSyscallABI32,
diff --git a/src/arch/x86/linux/se_workload.cc
b/src/arch/x86/linux/se_workload.cc
index 1eb244d..fd2bf86 100644
--- a/src/arch/x86/linux/se_workload.cc
+++ b/src/arch/x86/linux/se_workload.cc
@@ -97,12 +97,12 @@
EmuLinux::EmuLinux(const Params &p) : SEWorkload(p)
{}
-const std::vector<RegIndex> EmuLinux::SyscallABI64::ArgumentRegs = {
+const std::vector<RegId> EmuLinux::SyscallABI64::ArgumentRegs = {
int_reg::Rdi, int_reg::Rsi, int_reg::Rdx,
int_reg::R10, int_reg::R8, int_reg::R9
};
-const std::vector<RegIndex> EmuLinux::SyscallABI32::ArgumentRegs = {
+const std::vector<RegId> EmuLinux::SyscallABI32::ArgumentRegs = {
int_reg::Ebx, int_reg::Ecx, int_reg::Edx,
int_reg::Esi, int_reg::Edi, int_reg::Ebp
};
diff --git a/src/arch/x86/linux/se_workload.hh
b/src/arch/x86/linux/se_workload.hh
index b9acbcb..22c5d52 100644
--- a/src/arch/x86/linux/se_workload.hh
+++ b/src/arch/x86/linux/se_workload.hh
@@ -78,13 +78,13 @@
struct SyscallABI64 :
public GenericSyscallABI64, public X86Linux::SyscallABI
{
- static const std::vector<RegIndex> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
struct SyscallABI32 :
public GenericSyscallABI32, public X86Linux::SyscallABI
{
- static const std::vector<RegIndex> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
private:
diff --git a/src/sim/syscall_abi.hh b/src/sim/syscall_abi.hh
index d50286f..b91dc8e 100644
--- a/src/sim/syscall_abi.hh
+++ b/src/sim/syscall_abi.hh
@@ -67,10 +67,10 @@
// Read two registers and merge them into one value.
static uint64_t
- mergeRegs(ThreadContext *tc, RegIndex low_idx, RegIndex high_idx)
+ mergeRegs(ThreadContext *tc, const RegId &low_id, const RegId &high_id)
{
- RegVal low = tc->readIntReg(low_idx);
- RegVal high = tc->readIntReg(high_idx);
+ RegVal low = tc->getReg(low_id);
+ RegVal high = tc->getReg(high_id);
return insertBits(low, 63, 32, high);
}
};
@@ -91,7 +91,7 @@
{
panic_if(state >= ABI::ArgumentRegs.size(),
"Ran out of syscall argument registers.");
- return tc->readIntReg(ABI::ArgumentRegs[state++]);
+ return tc->getReg(ABI::ArgumentRegs[state++]);
}
};
@@ -107,7 +107,7 @@
{
panic_if(state >= ABI::ArgumentRegs.size(),
"Ran out of syscall argument registers.");
- return bits(tc->readIntReg(ABI::ArgumentRegs[state++]), 31, 0);
+ return bits(tc->getReg(ABI::ArgumentRegs[state++]), 31, 0);
}
};
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49774
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4bbe884fe01fe14d7f18574f494a831dee2996d3
Gerrit-Change-Number: 49774
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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