Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49773 )
Change subject: arch-riscv: Revamp float regs.
......................................................................
arch-riscv: Revamp float regs.
Change-Id: I6bb7a4f78e59082c3f783a5d4c2cb79f9c6df61f
---
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/float.hh
M src/arch/riscv/remote_gdb.cc
M src/arch/riscv/remote_gdb.hh
M src/arch/riscv/utility.hh
5 files changed, 97 insertions(+), 12 deletions(-)
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 5d920a5..bcecdc1 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -188,7 +188,7 @@
ISA::ISA(const Params &p) : BaseISA(p)
{
_regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
- _regClasses.emplace_back(NumFloatRegs, debug::FloatRegs);
+ _regClasses.emplace_back(float_reg::NumRegs, debug::FloatRegs);
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(2, debug::IntRegs); // Not applicable to RISCV
_regClasses.emplace_back(1, debug::IntRegs); // Not applicable to RISCV
@@ -209,8 +209,10 @@
}
// Second loop through the float registers.
- for (int i = 0; i < NumFloatRegs; ++i)
- tc->setFloatReg(i, src->readFloatReg(i));
+ for (int i = 0; i < float_reg::NumRegs; ++i) {
+ RegId reg(FloatRegClass, i);
+ tc->setReg(reg, src->getReg(reg));
+ }
// Lastly copy PC/NPC
tc->pcState(src->pcState());
diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 37b94e2..531914a 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -54,6 +54,7 @@
#include <vector>
#include "base/bitfield.hh"
+#include "cpu/reg_class.hh"
namespace gem5
{
@@ -90,9 +91,90 @@
static constexpr freg_t freg(float64_t f) { return f; }
static constexpr freg_t freg(uint_fast16_t f) { return {f}; }
-const int NumFloatRegs = 32;
+namespace float_reg
+{
-const std::vector<std::string> FloatRegNames = {
+enum : RegIndex
+{
+ _Ft0Idx,
+ _Ft1Idx,
+ _Ft2Idx,
+ _Ft3Idx,
+ _Ft4Idx,
+ _Ft5Idx,
+ _Ft6Idx,
+ _Ft7Idx,
+
+ _Fs0Idx,
+ _Fs1Idx,
+
+ _Fa0Idx,
+ _Fa1Idx,
+ _Fa2Idx,
+ _Fa3Idx,
+ _Fa4Idx,
+ _Fa5Idx,
+ _Fa6Idx,
+ _Fa7Idx,
+
+ _Fs2Idx,
+ _Fs3Idx,
+ _Fs4Idx,
+ _Fs5Idx,
+ _Fs6Idx,
+ _Fs7Idx,
+ _Fs8Idx,
+ _Fs9Idx,
+ _Fs10Idx,
+ _Fs11Idx,
+
+ _Ft8Idx,
+ _Ft9Idx,
+ _Ft10Idx,
+ _Ft11Idx,
+
+ NumRegs
+};
+
+inline constexpr RegId
+ Ft0(FloatRegClass, _Ft0Idx),
+ Ft1(FloatRegClass, _Ft1Idx),
+ Ft2(FloatRegClass, _Ft2Idx),
+ Ft3(FloatRegClass, _Ft3Idx),
+ Ft4(FloatRegClass, _Ft4Idx),
+ Ft5(FloatRegClass, _Ft5Idx),
+ Ft6(FloatRegClass, _Ft6Idx),
+ Ft7(FloatRegClass, _Ft7Idx),
+
+ Fs0(FloatRegClass, _Fs0Idx),
+ Fs1(FloatRegClass, _Fs1Idx),
+
+ Fa0(FloatRegClass, _Fa0Idx),
+ Fa1(FloatRegClass, _Fa1Idx),
+ Fa2(FloatRegClass, _Fa2Idx),
+ Fa3(FloatRegClass, _Fa3Idx),
+ Fa4(FloatRegClass, _Fa4Idx),
+ Fa5(FloatRegClass, _Fa5Idx),
+ Fa6(FloatRegClass, _Fa6Idx),
+ Fa7(FloatRegClass, _Fa7Idx),
+
+ Fs2(FloatRegClass, _Fs2Idx),
+ Fs3(FloatRegClass, _Fs3Idx),
+ Fs4(FloatRegClass, _Fs4Idx),
+ Fs5(FloatRegClass, _Fs5Idx),
+ Fs6(FloatRegClass, _Fs6Idx),
+ Fs7(FloatRegClass, _Fs7Idx),
+ Fs8(FloatRegClass, _Fs8Idx),
+ Fs9(FloatRegClass, _Fs9Idx),
+ Fs10(FloatRegClass, _Fs10Idx),
+ Fs11(FloatRegClass, _Fs11Idx),
+
+ Ft8(FloatRegClass, _Ft8Idx),
+ Ft9(FloatRegClass, _Ft9Idx),
+ Ft10(FloatRegClass, _Ft10Idx),
+ Ft11(FloatRegClass, _Ft11Idx);
+
+const std::vector<std::string> RegNames = {
"ft0", "ft1", "ft2", "ft3",
"ft4", "ft5", "ft6", "ft7",
"fs0", "fs1", "fa0", "fa1",
@@ -103,6 +185,7 @@
"ft8", "ft9", "ft10", "ft11"
};
+} // namespace float_reg
} // namespace RiscvISA
} // namespace gem5
diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index e730060..dc4421f 100644
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -197,8 +197,8 @@
r.pc = context->pcState().pc();
// Floating point registers
- for (int i = 0; i < NumFloatRegs; i++)
- r.fpu[i] = context->readFloatReg(i);
+ for (int i = 0; i < float_reg::NumRegs; i++)
+ r.fpu[i] = context->getReg(RegId(FloatRegClass, i));
r.fflags = context->readMiscRegNoEffect(
CSRData.at(CSR_FFLAGS).physIndex) & CSRMasks.at(CSR_FFLAGS);
r.frm = context->readMiscRegNoEffect(
@@ -307,8 +307,8 @@
context->pcState(r.pc);
// Floating point registers
- for (int i = 0; i < NumFloatRegs; i++)
- context->setFloatReg(i, r.fpu[i]);
+ for (int i = 0; i < float_reg::NumRegs; i++)
+ context->setReg(RegId(FloatRegClass, i), r.fpu[i]);
oldVal = context->readMiscRegNoEffect(
CSRData.at(CSR_FFLAGS).physIndex);
diff --git a/src/arch/riscv/remote_gdb.hh b/src/arch/riscv/remote_gdb.hh
index fab945f..ec8d62a 100644
--- a/src/arch/riscv/remote_gdb.hh
+++ b/src/arch/riscv/remote_gdb.hh
@@ -74,7 +74,7 @@
{
uint64_t gpr[int_reg::NumArchRegs];
uint64_t pc;
- uint64_t fpu[NumFloatRegs];
+ uint64_t fpu[float_reg::NumRegs];
uint32_t fflags;
uint32_t frm;
uint32_t fcsr;
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index 7ccbad0..8899288 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -122,12 +122,12 @@
}
return int_reg::RegNames[reg.index()];
} else {
- if (reg.index() >= NumFloatRegs) {
+ if (reg.index() >= float_reg::NumRegs) {
std::stringstream str;
str << "?? (f" << reg.index() << ')';
return str.str();
}
- return FloatRegNames[reg.index()];
+ return float_reg::RegNames[reg.index()];
}
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I6bb7a4f78e59082c3f783a5d4c2cb79f9c6df61f
Gerrit-Change-Number: 49773
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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