Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49777 )
Change subject: cpu: Switch to the (get|set)Reg API in the checker CPU.
......................................................................
cpu: Switch to the (get|set)Reg API in the checker CPU.
Change-Id: I7ab1319ae6fc6d0d5bc62322fbe92c7131ce6403
---
M src/arch/mips/se_workload.cc
M src/arch/mips/se_workload.hh
M src/cpu/checker/cpu_impl.hh
3 files changed, 18 insertions(+), 23 deletions(-)
diff --git a/src/arch/mips/se_workload.cc b/src/arch/mips/se_workload.cc
index 75e1ac1..8bd5146 100644
--- a/src/arch/mips/se_workload.cc
+++ b/src/arch/mips/se_workload.cc
@@ -33,8 +33,9 @@
namespace MipsISA
{
-const std::vector<int> SEWorkload::SyscallABI::ArgumentRegs = {
- 4, 5, 6, 7, 8, 9
+const std::vector<RegId> SEWorkload::SyscallABI::ArgumentRegs = {
+ int_reg::A0, int_reg::A1, int_reg::A2,
+ int_reg::A3, int_reg::T0, int_reg::T1
};
} // namespace MipsISA
diff --git a/src/arch/mips/se_workload.hh b/src/arch/mips/se_workload.hh
index 44d4ab0..9dbad33 100644
--- a/src/arch/mips/se_workload.hh
+++ b/src/arch/mips/se_workload.hh
@@ -59,7 +59,7 @@
struct SyscallABI : public GenericSyscallABI64
{
- static const std::vector<int> ArgumentRegs;
+ static const std::vector<RegId> ArgumentRegs;
};
};
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 5231802..83b0a07 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -585,19 +585,16 @@
case InvalidRegClass:
break;
case IntRegClass:
- thread->setIntReg(idx.index(), mismatch_val.as<RegVal>());
- break;
case FloatRegClass:
- thread->setFloatReg(idx.index(), mismatch_val.as<RegVal>());
+ case VecElemClass:
+ case CCRegClass:
+ thread->setReg(idx, mismatch_val.as<RegVal>());
break;
case VecRegClass:
- thread->setVecReg(idx,
mismatch_val.as<TheISA::VecRegContainer>());
- break;
- case VecElemClass:
- thread->setVecElem(idx, mismatch_val.as<RegVal>());
- break;
- case CCRegClass:
- thread->setCCReg(idx.index(), mismatch_val.as<RegVal>());
+ {
+ auto val = mismatch_val.as<TheISA::VecRegContainer>();
+ thread->setReg(idx, &val);
+ }
break;
case MiscRegClass:
thread->setMiscReg(idx.index(), mismatch_val.as<RegVal>());
@@ -615,19 +612,16 @@
case InvalidRegClass:
break;
case IntRegClass:
- thread->setIntReg(idx.index(), res.as<RegVal>());
- break;
case FloatRegClass:
- thread->setFloatReg(idx.index(), res.as<RegVal>());
+ case VecElemClass:
+ case CCRegClass:
+ thread->setReg(idx, res.as<RegVal>());
break;
case VecRegClass:
- thread->setVecReg(idx, res.as<TheISA::VecRegContainer>());
- break;
- case VecElemClass:
- thread->setVecElem(idx, res.as<RegVal>());
- break;
- case CCRegClass:
- thread->setCCReg(idx.index(), res.as<RegVal>());
+ {
+ auto val = res.as<TheISA::VecRegContainer>();
+ thread->setReg(idx, &val);
+ }
break;
case MiscRegClass:
// Try to get the proper misc register index for ARM here...
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49777
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7ab1319ae6fc6d0d5bc62322fbe92c7131ce6403
Gerrit-Change-Number: 49777
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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