Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49784 )
Change subject: arch,cpu: Store pointers to RegClass-es instead of
instances.
......................................................................
arch,cpu: Store pointers to RegClass-es instead of instances.
This lets us put the actual RegClass-es somewhere else and give them
names.
Change-Id: I51743d6956de632fa6498d3b5ef0a20939849464
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/cc.hh
M src/arch/arm/regs/int.hh
M src/arch/arm/regs/misc.hh
M src/arch/arm/regs/vec.hh
M src/arch/generic/isa.hh
M src/arch/mips/isa.cc
M src/arch/mips/regs/float.hh
M src/arch/mips/regs/int.hh
M src/arch/mips/regs/misc.hh
M src/arch/power/isa.cc
M src/arch/power/regs/float.hh
M src/arch/power/regs/int.hh
M src/arch/power/regs/misc.hh
M src/arch/riscv/isa.cc
M src/arch/riscv/regs/float.hh
M src/arch/riscv/regs/int.hh
M src/arch/riscv/regs/misc.hh
M src/arch/sparc/isa.cc
M src/arch/sparc/regs/float.hh
M src/arch/sparc/regs/int.hh
M src/arch/sparc/regs/misc.hh
M src/arch/x86/isa.cc
M src/arch/x86/regs/ccr.hh
M src/arch/x86/regs/float.hh
M src/arch/x86/regs/int.hh
M src/arch/x86/regs/misc.hh
M src/cpu/minor/dyn_inst.cc
M src/cpu/minor/scoreboard.hh
M src/cpu/o3/cpu.cc
M src/cpu/o3/inst_queue.cc
M src/cpu/o3/regfile.cc
M src/cpu/o3/rename_map.cc
M src/cpu/simple_thread.cc
M src/cpu/thread_context.cc
35 files changed, 301 insertions(+), 168 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 47f9c1f..8b476e12 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -42,6 +42,10 @@
#include "arch/arm/interrupts.hh"
#include "arch/arm/mmu.hh"
#include "arch/arm/pmu.hh"
+#include "arch/arm/regs/cc.hh"
+#include "arch/arm/regs/int.hh"
+#include "arch/arm/regs/misc.hh"
+#include "arch/arm/regs/vec.hh"
#include "arch/arm/self_debug.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlbi_op.hh"
@@ -50,12 +54,6 @@
#include "cpu/checker/cpu.hh"
#include "cpu/reg_class.hh"
#include "debug/Arm.hh"
-#include "debug/CCRegs.hh"
-#include "debug/FloatRegs.hh"
-#include "debug/IntRegs.hh"
-#include "debug/MiscRegs.hh"
-#include "debug/VecPredRegs.hh"
-#include "debug/VecRegs.hh"
#include "dev/arm/generic_timer.hh"
#include "dev/arm/gic_v3.hh"
#include "dev/arm/gic_v3_cpu_interface.hh"
@@ -70,37 +68,25 @@
namespace ArmISA
{
-class MiscRegClassOps : public RegClassOps
+namespace
{
- public:
- std::string
- regName(const RegId &id) const override
- {
- return miscRegName[id.index()];
- }
-} miscRegClassOps;
-VecElemRegClassOps<ArmISA::VecElem>
vecRegElemClassOps(NumVecElemPerVecReg);
-TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
-TypedRegClassOps<ArmISA::VecPredRegContainer> vecPredRegClassOps;
+/* Not applicable to ARM */
+RegClass floatRegClass(FloatRegClass, 0, debug::FloatRegs);
+
+} // anonymous namespace
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
- _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
- _regClasses.emplace_back(FloatRegClass, 0, debug::FloatRegs);
- _regClasses.emplace_back(VecRegClass, NumVecRegs, vecRegClassOps,
- debug::VecRegs, sizeof(VecRegContainer));
- _regClasses.emplace_back(VecElemClass,
- NumVecRegs * ArmISA::NumVecElemPerVecReg, vecRegElemClassOps,
- debug::VecRegs);
- _regClasses.emplace_back(VecPredRegClass, NumVecPredRegs,
- vecPredRegClassOps, debug::VecPredRegs,
- sizeof(VecPredRegContainer));
- _regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
- _regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, miscRegClassOps,
- debug::MiscRegs);
+ _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&floatRegClass);
+ _regClasses.push_back(&vecRegClass);
+ _regClasses.push_back(&vecElemClass);
+ _regClasses.push_back(&vecPredRegClass);
+ _regClasses.push_back(&ccRegClass);
+ _regClasses.push_back(&miscRegClass);
miscRegs[MISCREG_SCTLR_RST] = 0;
diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh
index 2aa55fa..7126e4e 100644
--- a/src/arch/arm/regs/cc.hh
+++ b/src/arch/arm/regs/cc.hh
@@ -39,6 +39,7 @@
#define __ARCH_ARM_REGS_CC_HH__
#include "cpu/reg_class.hh"
+#include "debug/CCRegs.hh"
namespace gem5
{
@@ -79,6 +80,9 @@
} // namespace cc_reg
+inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
+ debug::CCRegs);
+
enum ConditionCode
{
COND_EQ = 0,
diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh
index dcca500..9bc9100 100644
--- a/src/arch/arm/regs/int.hh
+++ b/src/arch/arm/regs/int.hh
@@ -46,6 +46,7 @@
#include "arch/arm/types.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
+#include "debug/IntRegs.hh"
#include "sim/core.hh"
namespace gem5
@@ -552,6 +553,9 @@
} // namespace int_reg
+inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+ debug::IntRegs);
+
static inline int
flattenIntRegModeIndex(int reg)
{
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 0e9825d..c2127b2 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -46,6 +46,8 @@
#include "arch/arm/regs/misc_types.hh"
#include "base/compiler.hh"
+#include "cpu/reg_class.hh"
+#include "debug/MiscRegs.hh"
#include "dev/arm/generic_timer_miscregs_types.hh"
namespace gem5
@@ -2186,6 +2188,21 @@
static_assert(sizeof(miscRegName) / sizeof(*miscRegName) ==
NUM_MISCREGS,
"The miscRegName array and NUM_MISCREGS are
inconsistent.");
+ class MiscRegClassOps : public RegClassOps
+ {
+ public:
+ std::string
+ regName(const RegId &id) const override
+ {
+ return miscRegName[id.index()];
+ }
+ };
+
+ static inline MiscRegClassOps miscRegClassOps;
+
+ inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
+ miscRegClassOps, debug::MiscRegs);
+
// This mask selects bits of the CPSR that actually go in the CondCodes
// integer register to allow renaming.
static const uint32_t CondCodesMask = 0xF00F0000;
diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh
index 6a7d6e4..fcb9375 100644
--- a/src/arch/arm/regs/vec.hh
+++ b/src/arch/arm/regs/vec.hh
@@ -44,6 +44,9 @@
#include "arch/arm/types.hh"
#include "arch/generic/vec_pred_reg.hh"
#include "arch/generic/vec_reg.hh"
+#include "cpu/reg_class.hh"
+#include "debug/VecPredRegs.hh"
+#include "debug/VecRegs.hh"
namespace gem5
{
@@ -90,6 +93,18 @@
const int PREDREG_FFR = 16;
const int PREDREG_UREG0 = 17;
+static inline VecElemRegClassOps<ArmISA::VecElem>
+ vecRegElemClassOps(NumVecElemPerVecReg);
+static inline TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
+static inline TypedRegClassOps<ArmISA::VecPredRegContainer>
vecPredRegClassOps;
+
+inline constexpr RegClass vecRegClass(VecRegClass, NumVecRegs,
vecRegClassOps,
+ debug::VecRegs, sizeof(VecRegContainer));
+inline constexpr RegClass vecElemClass(VecElemClass,
+ NumVecRegs * NumVecElemPerVecReg, vecRegElemClassOps,
debug::VecRegs);
+inline constexpr RegClass vecPredRegClass(VecPredRegClass, NumVecPredRegs,
+ vecPredRegClassOps, debug::VecPredRegs,
sizeof(VecPredRegContainer));
+
} // namespace ArmISA
} // namespace gem5
diff --git a/src/arch/generic/isa.hh b/src/arch/generic/isa.hh
index 9b5e497..3a7b31b 100644
--- a/src/arch/generic/isa.hh
+++ b/src/arch/generic/isa.hh
@@ -53,7 +53,7 @@
class BaseISA : public SimObject
{
public:
- typedef std::vector<RegClass> RegClasses;
+ typedef std::vector<const RegClass *> RegClasses;
protected:
using SimObject::SimObject;
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 81b65b2..1a1098e 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -38,10 +38,7 @@
#include "cpu/base.hh"
#include "cpu/reg_class.hh"
#include "cpu/thread_context.hh"
-#include "debug/FloatRegs.hh"
-#include "debug/IntRegs.hh"
#include "debug/MipsPRA.hh"
-#include "debug/MiscRegs.hh"
#include "params/MipsISA.hh"
namespace gem5
@@ -97,20 +94,27 @@
"LLFlag"
};
+namespace
+{
+
+/* Not applicable to MIPS. */
+constexpr RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
+constexpr RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
+constexpr RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
+constexpr RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+
+} // anonymous namespace
+
ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
numVpes(p.num_vpes)
{
- _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
- _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
-
- /* Not applicable to MIPS. */
- _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
- _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
-
- _regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
+ _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&floatRegClass);
+ _regClasses.push_back(&vecRegClass);
+ _regClasses.push_back(&vecElemClass);
+ _regClasses.push_back(&vecPredRegClass);
+ _regClasses.push_back(&ccRegClass);
+ _regClasses.push_back(&miscRegClass);
miscRegFile.resize(misc_reg::NumRegs);
bankType.resize(misc_reg::NumRegs);
diff --git a/src/arch/mips/regs/float.hh b/src/arch/mips/regs/float.hh
index d18aa96..7238e20 100644
--- a/src/arch/mips/regs/float.hh
+++ b/src/arch/mips/regs/float.hh
@@ -32,6 +32,9 @@
#include <cstdint>
+#include "cpu/reg_class.hh"
+#include "debug/FloatRegs.hh"
+
namespace gem5
{
namespace MipsISA
@@ -146,6 +149,9 @@
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
+inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
} // namespace MipsISA
} // namespace gem5
diff --git a/src/arch/mips/regs/int.hh b/src/arch/mips/regs/int.hh
index 0f65854..861d8b3 100644
--- a/src/arch/mips/regs/int.hh
+++ b/src/arch/mips/regs/int.hh
@@ -31,6 +31,7 @@
#define __ARCH_MIPS_REGS_INT_HH__
#include "cpu/reg_class.hh"
+#include "debug/IntRegs.hh"
namespace gem5
{
@@ -199,6 +200,10 @@
&SyscallSuccess = A3;
} // namespace int_reg
+
+inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+ debug::IntRegs);
+
} // namespace MipsISA
} // namespace gem5
diff --git a/src/arch/mips/regs/misc.hh b/src/arch/mips/regs/misc.hh
index 7bb0886..90251d6 100644
--- a/src/arch/mips/regs/misc.hh
+++ b/src/arch/mips/regs/misc.hh
@@ -30,6 +30,9 @@
#ifndef __ARCH_MIPS_REGS_MISC_HH__
#define __ARCH_MIPS_REGS_MISC_HH__
+#include "cpu/reg_class.hh"
+#include "debug/MiscRegs.hh"
+
namespace gem5
{
namespace MipsISA
@@ -196,6 +199,10 @@
};
} // namespace misc_reg
+
+inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
+ debug::MiscRegs);
+
} // namespace MipsISA
} // namespace gem5
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
index 38d0d17..a5916b5 100644
--- a/src/arch/power/isa.cc
+++ b/src/arch/power/isa.cc
@@ -41,9 +41,6 @@
#include "arch/power/regs/int.hh"
#include "arch/power/regs/misc.hh"
#include "cpu/thread_context.hh"
-#include "debug/FloatRegs.hh"
-#include "debug/IntRegs.hh"
-#include "debug/MiscRegs.hh"
#include "params/PowerISA.hh"
namespace gem5
@@ -52,16 +49,25 @@
namespace PowerISA
{
+namespace
+{
+
+RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
+RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+
+} // anonymous namespace
+
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
- _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
- _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
- _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
- _regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
+ _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&floatRegClass);
+ _regClasses.push_back(&vecRegClass);
+ _regClasses.push_back(&vecElemClass);
+ _regClasses.push_back(&vecPredRegClass);
+ _regClasses.push_back(&ccRegClass);
+ _regClasses.push_back(&miscRegClass);
clear();
}
diff --git a/src/arch/power/regs/float.hh b/src/arch/power/regs/float.hh
index ce31c3a..11f1aab 100644
--- a/src/arch/power/regs/float.hh
+++ b/src/arch/power/regs/float.hh
@@ -29,6 +29,9 @@
#ifndef __ARCH_POWER_REGS_FLOAT_HH__
#define __ARCH_POWER_REGS_FLOAT_HH__
+#include "cpu/reg_class.hh"
+#include "debug/FloatRegs.hh"
+
namespace gem5
{
@@ -42,6 +45,10 @@
const int NumRegs = NumArchRegs;
} // namespace float_reg
+
+inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
} // namespace PowerISA
} // namespace gem5
diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh
index 324062d..7a302fe 100644
--- a/src/arch/power/regs/int.hh
+++ b/src/arch/power/regs/int.hh
@@ -31,6 +31,7 @@
#define __ARCH_POWER_REGS_INT_HH__
#include "cpu/reg_class.hh"
+#include "debug/IntRegs.hh"
namespace gem5
{
@@ -139,6 +140,9 @@
} // namespace int_reg
+inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+ debug::IntRegs);
+
// Semantically meaningful register indices
inline constexpr auto
&ReturnValueReg = int_reg::R3,
diff --git a/src/arch/power/regs/misc.hh b/src/arch/power/regs/misc.hh
index dd59ea8..1ab8e42 100644
--- a/src/arch/power/regs/misc.hh
+++ b/src/arch/power/regs/misc.hh
@@ -31,6 +31,8 @@
#define __ARCH_POWER_MISCREGS_HH__
#include "base/bitunion.hh"
+#include "cpu/reg_class.hh"
+#include "debug/MiscRegs.hh"
namespace gem5
{
@@ -46,6 +48,9 @@
const char * const miscRegName[NUM_MISCREGS] = {
};
+inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
+ debug::MiscRegs);
+
BitUnion32(Cr)
SubBitUnion(cr0, 31, 28)
Bitfield<31> lt;
diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 1e47916..3be7457 100644
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -45,9 +45,6 @@
#include "base/compiler.hh"
#include "cpu/base.hh"
#include "debug/Checkpoint.hh"
-#include "debug/FloatRegs.hh"
-#include "debug/IntRegs.hh"
-#include "debug/MiscRegs.hh"
#include "debug/RiscvMisc.hh"
#include "params/RiscvISA.hh"
#include "sim/pseudo_inst.hh"
@@ -185,19 +182,26 @@
[MISCREG_FRM] = "FRM",
}};
+namespace
+{
+
+/* Not applicable to RISCV */
+RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
+RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+
+} // anonymous namespace
+
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
- _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
-
- /* Not applicable to RISCV */
- _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
- _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
-
- _regClasses.emplace_back(MiscRegClass, NUM_MISCREGS, debug::MiscRegs);
+ _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&floatRegClass);
+ _regClasses.push_back(&vecRegClass);
+ _regClasses.push_back(&vecElemClass);
+ _regClasses.push_back(&vecPredRegClass);
+ _regClasses.push_back(&ccRegClass);
+ _regClasses.push_back(&miscRegClass);
miscRegFile.resize(NUM_MISCREGS);
clear();
diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh
index 531914a..6627d1d 100644
--- a/src/arch/riscv/regs/float.hh
+++ b/src/arch/riscv/regs/float.hh
@@ -55,6 +55,7 @@
#include "base/bitfield.hh"
#include "cpu/reg_class.hh"
+#include "debug/FloatRegs.hh"
namespace gem5
{
@@ -186,6 +187,10 @@
};
} // namespace float_reg
+
+inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
} // namespace RiscvISA
} // namespace gem5
diff --git a/src/arch/riscv/regs/int.hh b/src/arch/riscv/regs/int.hh
index 5d60416..fa5e521 100644
--- a/src/arch/riscv/regs/int.hh
+++ b/src/arch/riscv/regs/int.hh
@@ -50,6 +50,7 @@
#include <vector>
#include "cpu/reg_class.hh"
+#include "debug/IntRegs.hh"
namespace gem5
{
@@ -126,6 +127,9 @@
} // namespace int_reg
+inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+ debug::IntRegs);
+
// Semantically meaningful register indices
inline constexpr auto
&ReturnAddrReg = int_reg::Ra,
diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh
index 5bfcbe1..8337d61 100644
--- a/src/arch/riscv/regs/misc.hh
+++ b/src/arch/riscv/regs/misc.hh
@@ -53,6 +53,8 @@
#include "arch/generic/vec_reg.hh"
#include "base/bitunion.hh"
#include "base/types.hh"
+#include "cpu/reg_class.hh"
+#include "debug/MiscRegs.hh"
namespace gem5
{
@@ -190,6 +192,9 @@
NUM_MISCREGS
};
+inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
+ debug::MiscRegs);
+
enum CSRIndex
{
CSR_USTATUS = 0x000,
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index c3fde76..a675d94 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -39,9 +39,6 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "debug/FloatRegs.hh"
-#include "debug/IntRegs.hh"
-#include "debug/MiscRegs.hh"
#include "debug/Timer.hh"
#include "params/SparcISA.hh"
@@ -68,19 +65,27 @@
static const PSTATE PstateMask = buildPstateMask();
+namespace
+{
+
+/* Not applicable for SPARC */
+RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
+RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
+
+} // anonymous namespace
+
ISA::ISA(const Params &p) : BaseISA(p)
{
- _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
- _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
+ _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&floatRegClass);
+ _regClasses.push_back(&vecRegClass);
+ _regClasses.push_back(&vecElemClass);
+ _regClasses.push_back(&vecPredRegClass);
+ _regClasses.push_back(&ccRegClass);
+ _regClasses.push_back(&miscRegClass);
- /* Not applicable for SPARC */
- _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
- _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(CCRegClass, 0, debug::IntRegs);
-
- _regClasses.emplace_back(MiscRegClass, NumMiscRegs, debug::MiscRegs);
clear();
}
diff --git a/src/arch/sparc/regs/float.hh b/src/arch/sparc/regs/float.hh
index 78f4db5..8398b73 100644
--- a/src/arch/sparc/regs/float.hh
+++ b/src/arch/sparc/regs/float.hh
@@ -29,6 +29,9 @@
#ifndef __ARCH_SPARC_REGS_FLOAT_HH__
#define __ARCH_SPARC_REGS_FLOAT_HH__
+#include "cpu/reg_class.hh"
+#include "debug/FloatRegs.hh"
+
namespace gem5
{
@@ -42,6 +45,10 @@
const int NumArchRegs = NumRegs;
} // namespace float_reg
+
+inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
} // namespace SparcISA
} // namespace gem5
diff --git a/src/arch/sparc/regs/int.hh b/src/arch/sparc/regs/int.hh
index 98c2a93..53d7937 100644
--- a/src/arch/sparc/regs/int.hh
+++ b/src/arch/sparc/regs/int.hh
@@ -31,6 +31,7 @@
#include "arch/sparc/sparc_traits.hh"
#include "cpu/reg_class.hh"
+#include "debug/IntRegs.hh"
namespace gem5
{
@@ -142,6 +143,9 @@
} // namespace int_reg
+inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+ debug::IntRegs);
+
// the rest of these depend on the ABI
inline constexpr auto
&ReturnAddressReg = int_reg::I7, // post call, precall is 15
diff --git a/src/arch/sparc/regs/misc.hh b/src/arch/sparc/regs/misc.hh
index 1620c60..0f008c3 100644
--- a/src/arch/sparc/regs/misc.hh
+++ b/src/arch/sparc/regs/misc.hh
@@ -31,6 +31,8 @@
#include "base/bitunion.hh"
#include "base/types.hh"
+#include "cpu/reg_class.hh"
+#include "debug/MiscRegs.hh"
namespace gem5
{
@@ -172,6 +174,9 @@
const int NumMiscRegs = MISCREG_NUMMISCREGS;
+inline constexpr RegClass miscRegClass(MiscRegClass, NumMiscRegs,
+ debug::MiscRegs);
+
} // namespace SparcISA
} // namespace gem5
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 57dcd53..dc68cde 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -31,15 +31,12 @@
#include "arch/x86/decoder.hh"
#include "arch/x86/mmu.hh"
#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
#include "base/compiler.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "debug/CCRegs.hh"
-#include "debug/FloatRegs.hh"
-#include "debug/IntRegs.hh"
-#include "debug/MiscRegs.hh"
#include "params/X86ISA.hh"
#include "sim/serialize.hh"
@@ -141,22 +138,28 @@
regVal[misc_reg::ApicBase] = lApicBase;
}
+namespace
+{
+
+/* Not applicable to X86 */
+RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
+RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
+RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
+
+} // anonymous namespace
+
ISA::ISA(const X86ISAParams &p) : BaseISA(p), vendorString(p.vendor_string)
{
fatal_if(vendorString.size() != 12,
"CPUID vendor string must be 12 characters\n");
- _regClasses.emplace_back(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
- _regClasses.emplace_back(FloatRegClass, float_reg::NumRegs,
- debug::FloatRegs);
-
- /* Not applicable to X86 */
- _regClasses.emplace_back(VecRegClass, 1, debug::IntRegs);
- _regClasses.emplace_back(VecElemClass, 2, debug::IntRegs);
- _regClasses.emplace_back(VecPredRegClass, 1, debug::IntRegs);
-
- _regClasses.emplace_back(CCRegClass, cc_reg::NumRegs, debug::CCRegs);
- _regClasses.emplace_back(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
+ _regClasses.push_back(&intRegClass);
+ _regClasses.push_back(&floatRegClass);
+ _regClasses.push_back(&vecRegClass);
+ _regClasses.push_back(&vecElemClass);
+ _regClasses.push_back(&vecPredRegClass);
+ _regClasses.push_back(&ccRegClass);
+ _regClasses.push_back(&miscRegClass);
clear();
}
diff --git a/src/arch/x86/regs/ccr.hh b/src/arch/x86/regs/ccr.hh
index 1073edd..44cbc49 100644
--- a/src/arch/x86/regs/ccr.hh
+++ b/src/arch/x86/regs/ccr.hh
@@ -39,6 +39,7 @@
#define __ARCH_X86_REGS_CCR_HH__
#include "cpu/reg_class.hh"
+#include "debug/CCRegs.hh"
namespace gem5
{
@@ -66,6 +67,10 @@
Ezf(CCRegClass, _EzfIdx);
} // namespace cc_reg
+
+inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
+ debug::CCRegs);
+
} // namespace X86ISA
} // namespace gem5
diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh
index 45e2169..f6190f9 100644
--- a/src/arch/x86/regs/float.hh
+++ b/src/arch/x86/regs/float.hh
@@ -40,6 +40,8 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
+#include "cpu/reg_class.hh"
+#include "debug/FloatRegs.hh"
namespace gem5
{
@@ -161,6 +163,9 @@
} // namespace float_reg
+inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
+ debug::FloatRegs);
+
} // namespace X86ISA
} // namespace gem5
diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh
index 445e6a8..4201ffa 100644
--- a/src/arch/x86/regs/int.hh
+++ b/src/arch/x86/regs/int.hh
@@ -42,6 +42,7 @@
#include "base/bitunion.hh"
#include "base/logging.hh"
#include "cpu/reg_class.hh"
+#include "debug/IntRegs.hh"
namespace gem5
{
@@ -145,6 +146,9 @@
} // namespace int_reg
+inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
+ debug::IntRegs);
+
// This needs to be large enough to miss all the other bits of an index.
inline constexpr RegIndex IntFoldBit = 1 << 6;
diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh
index f9c526b..aa854e9 100644
--- a/src/arch/x86/regs/misc.hh
+++ b/src/arch/x86/regs/misc.hh
@@ -42,6 +42,8 @@
#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"
#include "base/logging.hh"
+#include "cpu/reg_class.hh"
+#include "debug/MiscRegs.hh"
//These get defined in some system headers (at least termbits.h). That
confuses
//things here significantly.
@@ -536,6 +538,9 @@
} // namespace misc_reg
+inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
+ debug::MiscRegs);
+
/**
* A type to describe the condition code bits of the RFLAGS register,
* plus two flags, EZF and ECF, which are only visible to microcode.
diff --git a/src/cpu/minor/dyn_inst.cc b/src/cpu/minor/dyn_inst.cc
index 0c87732..6dd5133 100644
--- a/src/cpu/minor/dyn_inst.cc
+++ b/src/cpu/minor/dyn_inst.cc
@@ -142,7 +142,7 @@
printRegName(std::ostream &os, const RegId& reg,
const BaseISA::RegClasses ®_classes)
{
- const auto ®_class = reg_classes.at(reg.classValue());
+ const auto ®_class = *reg_classes.at(reg.classValue());
switch (reg.classValue()) {
case InvalidRegClass:
os << 'z';
diff --git a/src/cpu/minor/scoreboard.hh b/src/cpu/minor/scoreboard.hh
index 18e1f5a..30ca166 100644
--- a/src/cpu/minor/scoreboard.hh
+++ b/src/cpu/minor/scoreboard.hh
@@ -111,11 +111,11 @@
Named(name),
regClasses(reg_classes),
intRegOffset(0),
- floatRegOffset(intRegOffset + reg_classes.at(IntRegClass).size()),
- ccRegOffset(floatRegOffset + reg_classes.at(FloatRegClass).size()),
- vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass).size()),
- vecPredRegOffset(vecRegOffset +
reg_classes.at(VecElemClass).size()),
- numRegs(vecPredRegOffset + reg_classes.at(VecPredRegClass).size()),
+ floatRegOffset(intRegOffset + reg_classes.at(IntRegClass)->size()),
+ ccRegOffset(floatRegOffset +
reg_classes.at(FloatRegClass)->size()),
+ vecRegOffset(ccRegOffset + reg_classes.at(CCRegClass)->size()),
+ vecPredRegOffset(vecRegOffset +
reg_classes.at(VecElemClass)->size()),
+ numRegs(vecPredRegOffset +
reg_classes.at(VecPredRegClass)->size()),
numResults(numRegs, 0),
numUnpredictableResults(numRegs, 0),
fuIndices(numRegs, 0),
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 4442a84..53fd9d4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -194,19 +194,20 @@
const auto ®Classes = params.isa[0]->regClasses();
assert(params.numPhysIntRegs >=
- numThreads * regClasses.at(IntRegClass).size());
+ numThreads * regClasses.at(IntRegClass)->size());
assert(params.numPhysFloatRegs >=
- numThreads * regClasses.at(FloatRegClass).size());
+ numThreads * regClasses.at(FloatRegClass)->size());
assert(params.numPhysVecRegs >=
- numThreads * regClasses.at(VecRegClass).size());
+ numThreads * regClasses.at(VecRegClass)->size());
assert(params.numPhysVecPredRegs >=
- numThreads * regClasses.at(VecPredRegClass).size());
+ numThreads * regClasses.at(VecPredRegClass)->size());
assert(params.numPhysCCRegs >=
- numThreads * regClasses.at(CCRegClass).size());
+ numThreads * regClasses.at(CCRegClass)->size());
// Just make this a warning and go ahead anyway, to keep from having to
// add checks everywhere.
- warn_if(regClasses.at(CCRegClass).size() == 0 &&
params.numPhysCCRegs != 0,
+ warn_if(regClasses.at(CCRegClass)->size() == 0 &&
+ params.numPhysCCRegs != 0,
"Non-zero number of physical CC regs specified, even though\n"
" ISA does not use them.");
@@ -225,7 +226,7 @@
for (ThreadID tid = 0; tid < active_threads; tid++) {
for (auto type = (RegClassType)0; type <= CCRegClass;
type = (RegClassType)(type + 1)) {
- for (auto &id: regClasses.at(type)) {
+ for (auto &id: *regClasses.at(type)) {
// Note that we can't use the rename() method because we
don't
// want special treatment for the zero register at this
point
PhysRegIdPtr phys_reg = freeList.getReg(type);
@@ -691,7 +692,7 @@
for (auto type = (RegClassType)0; type <= CCRegClass;
type = (RegClassType)(type + 1)) {
- for (auto &id: regClasses.at(type)) {
+ for (auto &id: *regClasses.at(type)) {
PhysRegIdPtr phys_reg = freeList.getReg(type);
renameMap[tid].setEntry(id, phys_reg);
scoreboard.setReg(phys_reg);
diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc
index a7becc7..b4387d1 100644
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -105,8 +105,8 @@
numPhysRegs = params.numPhysIntRegs + params.numPhysFloatRegs +
params.numPhysVecRegs +
params.numPhysVecRegs * (
- reg_classes.at(VecElemClass).size() /
- reg_classes.at(VecRegClass).size()) +
+ reg_classes.at(VecElemClass)->size() /
+ reg_classes.at(VecRegClass)->size()) +
params.numPhysVecPredRegs +
params.numPhysCCRegs;
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index 1a20fe9..b557fef 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -55,20 +55,21 @@
unsigned _numPhysicalVecPredRegs,
unsigned _numPhysicalCCRegs,
const BaseISA::RegClasses ®_classes)
- : intRegFile(reg_classes.at(IntRegClass), _numPhysicalIntRegs),
- floatRegFile(reg_classes.at(FloatRegClass), _numPhysicalFloatRegs),
- vectorRegFile(reg_classes.at(VecRegClass), _numPhysicalVecRegs),
- vectorElemRegFile(reg_classes.at(VecElemClass), _numPhysicalVecRegs
* (
- reg_classes.at(VecElemClass).size() /
- reg_classes.at(VecRegClass).size())),
- vecPredRegFile(reg_classes.at(VecPredRegClass),
_numPhysicalVecPredRegs),
- ccRegFile(reg_classes.at(CCRegClass), _numPhysicalCCRegs),
+ : intRegFile(*reg_classes.at(IntRegClass), _numPhysicalIntRegs),
+ floatRegFile(*reg_classes.at(FloatRegClass), _numPhysicalFloatRegs),
+ vectorRegFile(*reg_classes.at(VecRegClass), _numPhysicalVecRegs),
+ vectorElemRegFile(*reg_classes.at(VecElemClass), _numPhysicalVecRegs
* (
+ reg_classes.at(VecElemClass)->size() /
+ reg_classes.at(VecRegClass)->size())),
+ vecPredRegFile(*reg_classes.at(VecPredRegClass),
+ _numPhysicalVecPredRegs),
+ ccRegFile(*reg_classes.at(CCRegClass), _numPhysicalCCRegs),
numPhysicalIntRegs(_numPhysicalIntRegs),
numPhysicalFloatRegs(_numPhysicalFloatRegs),
numPhysicalVecRegs(_numPhysicalVecRegs),
numPhysicalVecElemRegs(_numPhysicalVecRegs * (
- reg_classes.at(VecElemClass).size() /
- reg_classes.at(VecRegClass).size())),
+ reg_classes.at(VecElemClass)->size() /
+ reg_classes.at(VecRegClass)->size())),
numPhysicalVecPredRegs(_numPhysicalVecPredRegs),
numPhysicalCCRegs(_numPhysicalCCRegs),
totalNumRegs(_numPhysicalIntRegs
@@ -116,7 +117,7 @@
}
// Misc regs have a fixed mapping but still need PhysRegIds.
- for (phys_reg = 0; phys_reg < reg_classes.at(MiscRegClass).size();
+ for (phys_reg = 0; phys_reg < reg_classes.at(MiscRegClass)->size();
phys_reg++) {
miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
}
diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc
index 4b3a010..4682357 100644
--- a/src/cpu/o3/rename_map.cc
+++ b/src/cpu/o3/rename_map.cc
@@ -114,7 +114,7 @@
regFile = _regFile;
for (int i = 0; i < renameMaps.size(); i++)
- renameMaps[i].init(regClasses.at(i), &(freeList->freeLists[i]));
+ renameMaps[i].init(*regClasses.at(i), &(freeList->freeLists[i]));
}
bool
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index ab5efd3..cac5d6a 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -70,12 +70,12 @@
BaseISA *_isa)
: ThreadState(_cpu, _thread_num, _process),
regFiles{{
- {_isa->regClasses().at(IntRegClass)},
- {_isa->regClasses().at(FloatRegClass)},
- {_isa->regClasses().at(VecRegClass)},
- {_isa->regClasses().at(VecElemClass)},
- {_isa->regClasses().at(VecPredRegClass)},
- {_isa->regClasses().at(CCRegClass)}
+ {*_isa->regClasses().at(IntRegClass)},
+ {*_isa->regClasses().at(FloatRegClass)},
+ {*_isa->regClasses().at(VecRegClass)},
+ {*_isa->regClasses().at(VecElemClass)},
+ {*_isa->regClasses().at(VecPredRegClass)},
+ {*_isa->regClasses().at(CCRegClass)}
}},
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc
index 4a60d00..4985d11 100644
--- a/src/cpu/thread_context.cc
+++ b/src/cpu/thread_context.cc
@@ -65,7 +65,7 @@
DPRINTF(Context, "Comparing thread contexts\n");
// First loop through the integer registers.
- for (auto &id: regClasses.at(IntRegClass)) {
+ for (auto &id: *regClasses.at(IntRegClass)) {
RegVal t1 = one->getReg(id);
RegVal t2 = two->getReg(id);
if (t1 != t2)
@@ -74,7 +74,7 @@
}
// Then loop through the floating point registers.
- for (auto &id: regClasses.at(FloatRegClass)) {
+ for (auto &id: *regClasses.at(FloatRegClass)) {
RegVal t1 = one->getReg(id);
RegVal t2 = two->getReg(id);
if (t1 != t2)
@@ -83,34 +83,34 @@
}
// Then loop through the vector registers.
- const auto &vec_class = regClasses.at(VecRegClass);
- std::vector<uint8_t> vec1(vec_class.regBytes());
- std::vector<uint8_t> vec2(vec_class.regBytes());
- for (auto &id: regClasses.at(VecRegClass)) {
+ const auto *vec_class = regClasses.at(VecRegClass);
+ std::vector<uint8_t> vec1(vec_class->regBytes());
+ std::vector<uint8_t> vec2(vec_class->regBytes());
+ for (auto &id: *regClasses.at(VecRegClass)) {
one->getReg(id, vec1.data());
two->getReg(id, vec2.data());
if (vec1 != vec2) {
panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
- id.index(), vec_class.valString(vec1.data()),
- vec_class.valString(vec2.data()));
+ id.index(), vec_class->valString(vec1.data()),
+ vec_class->valString(vec2.data()));
}
}
// Then loop through the predicate registers.
- const auto &vec_pred_class = regClasses.at(VecPredRegClass);
- std::vector<uint8_t> pred1(vec_pred_class.regBytes());
- std::vector<uint8_t> pred2(vec_pred_class.regBytes());
- for (auto &id: regClasses.at(VecPredRegClass)) {
+ const auto *vec_pred_class = regClasses.at(VecPredRegClass);
+ std::vector<uint8_t> pred1(vec_pred_class->regBytes());
+ std::vector<uint8_t> pred2(vec_pred_class->regBytes());
+ for (auto &id: *regClasses.at(VecPredRegClass)) {
one->getReg(id, pred1.data());
two->getReg(id, pred2.data());
if (pred1 != pred2) {
panic("Pred reg idx %d doesn't match, one: %s, two: %s",
- id.index(), vec_pred_class.valString(pred1.data()),
- vec_pred_class.valString(pred2.data()));
+ id.index(), vec_pred_class->valString(pred1.data()),
+ vec_pred_class->valString(pred2.data()));
}
}
- for (int i = 0; i < regClasses.at(MiscRegClass).size(); ++i) {
+ for (int i = 0; i < regClasses.at(MiscRegClass)->size(); ++i) {
RegVal t1 = one->readMiscRegNoEffect(i);
RegVal t2 = two->readMiscRegNoEffect(i);
if (t1 != t2)
@@ -119,7 +119,7 @@
}
// loop through the Condition Code registers.
- for (auto &id: regClasses.at(CCRegClass)) {
+ for (auto &id: *regClasses.at(CCRegClass)) {
RegVal t1 = one->getReg(id);
RegVal t2 = two->getReg(id);
if (t1 != t2)
@@ -215,36 +215,36 @@
auto &nc_tc = const_cast<ThreadContext &>(tc);
const auto ®Classes = nc_tc.getIsaPtr()->regClasses();
- const size_t numFloats = regClasses.at(FloatRegClass).size();
+ const size_t numFloats = regClasses.at(FloatRegClass)->size();
RegVal floatRegs[numFloats];
- for (auto &id: regClasses.at(FloatRegClass))
+ for (auto &id: *regClasses.at(FloatRegClass))
floatRegs[id.index()] = tc.getRegFlat(id);
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamOut(cp, "floatRegs.i", floatRegs, numFloats);
- const size_t numVecs = regClasses.at(VecRegClass).size();
+ const size_t numVecs = regClasses.at(VecRegClass)->size();
std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
- for (auto &id: regClasses.at(VecRegClass))
+ for (auto &id: *regClasses.at(VecRegClass))
tc.getRegFlat(id, &vecRegs[id.index()]);
SERIALIZE_CONTAINER(vecRegs);
- const size_t numPreds = regClasses.at(VecPredRegClass).size();
+ const size_t numPreds = regClasses.at(VecPredRegClass)->size();
std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
- for (auto &id: regClasses.at(VecPredRegClass))
+ for (auto &id: *regClasses.at(VecPredRegClass))
tc.getRegFlat(id, &vecPredRegs[id.index()]);
SERIALIZE_CONTAINER(vecPredRegs);
- const size_t numInts = regClasses.at(IntRegClass).size();
+ const size_t numInts = regClasses.at(IntRegClass)->size();
RegVal intRegs[numInts];
- for (auto &id: regClasses.at(IntRegClass))
+ for (auto &id: *regClasses.at(IntRegClass))
intRegs[id.index()] = tc.getRegFlat(id);
SERIALIZE_ARRAY(intRegs, numInts);
- const size_t numCcs = regClasses.at(CCRegClass).size();
+ const size_t numCcs = regClasses.at(CCRegClass)->size();
if (numCcs) {
RegVal ccRegs[numCcs];
- for (auto &id: regClasses.at(CCRegClass))
+ for (auto &id: *regClasses.at(CCRegClass))
ccRegs[id.index()] = tc.getRegFlat(id);
SERIALIZE_ARRAY(ccRegs, numCcs);
}
@@ -259,37 +259,37 @@
{
const auto ®Classes = tc.getIsaPtr()->regClasses();
- const size_t numFloats = regClasses.at(FloatRegClass).size();
+ const size_t numFloats = regClasses.at(FloatRegClass)->size();
RegVal floatRegs[numFloats];
// This is a bit ugly, but needed to maintain backwards
// compatibility.
arrayParamIn(cp, "floatRegs.i", floatRegs, numFloats);
- for (auto &id: regClasses.at(FloatRegClass))
+ for (auto &id: *regClasses.at(FloatRegClass))
tc.setRegFlat(id, floatRegs[id.index()]);
- const size_t numVecs = regClasses.at(VecRegClass).size();
+ const size_t numVecs = regClasses.at(VecRegClass)->size();
std::vector<TheISA::VecRegContainer> vecRegs(numVecs);
UNSERIALIZE_CONTAINER(vecRegs);
- for (auto &id: regClasses.at(VecRegClass))
+ for (auto &id: *regClasses.at(VecRegClass))
tc.setRegFlat(id, &vecRegs[id.index()]);
- const size_t numPreds = regClasses.at(VecPredRegClass).size();
+ const size_t numPreds = regClasses.at(VecPredRegClass)->size();
std::vector<TheISA::VecPredRegContainer> vecPredRegs(numPreds);
UNSERIALIZE_CONTAINER(vecPredRegs);
- for (auto &id: regClasses.at(VecPredRegClass))
+ for (auto &id: *regClasses.at(VecPredRegClass))
tc.setRegFlat(id, &vecPredRegs[id.index()]);
- const size_t numInts = regClasses.at(IntRegClass).size();
+ const size_t numInts = regClasses.at(IntRegClass)->size();
RegVal intRegs[numInts];
UNSERIALIZE_ARRAY(intRegs, numInts);
- for (auto &id: regClasses.at(IntRegClass))
+ for (auto &id: *regClasses.at(IntRegClass))
tc.setRegFlat(id, intRegs[id.index()]);
- const size_t numCcs = regClasses.at(CCRegClass).size();
+ const size_t numCcs = regClasses.at(CCRegClass)->size();
if (numCcs) {
RegVal ccRegs[numCcs];
UNSERIALIZE_ARRAY(ccRegs, numCcs);
- for (auto &id: regClasses.at(CCRegClass))
+ for (auto &id: *regClasses.at(CCRegClass))
tc.setRegFlat(id, ccRegs[id.index()]);
}
--
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