Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/49786 )
Change subject: arch,cpu: Keep a RegClass pointer in RegId instead of a
RegClassType.
......................................................................
arch,cpu: Keep a RegClass pointer in RegId instead of a RegClassType.
This makes it easy to get access to the RegClass that goes with a
register without having to look it up in a separate structure.
Change-Id: I4cfff2069d63f3c1c3fb0fea5dee3baf357bd478
---
M src/arch/arm/isa/operands.isa
M src/arch/arm/tracers/tarmac_record.cc
M src/arch/arm/tracers/tarmac_record.hh
M src/arch/arm/tracers/tarmac_record_v8.cc
M src/arch/arm/tracers/tarmac_record_v8.hh
M src/arch/arm/utility.cc
M src/arch/isa_parser/operand_types.py
M src/arch/mips/isa/operands.isa
M src/arch/power/isa/includes.isa
M src/arch/riscv/isa/operands.isa
M src/arch/sparc/isa/includes.isa
M src/arch/sparc/isa/operands.isa
M src/arch/x86/isa/includes.isa
M src/arch/x86/isa/operands.isa
M src/cpu/SConscript
M src/cpu/o3/regfile.cc
M src/cpu/reg_class.hh
17 files changed, 112 insertions(+), 148 deletions(-)
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 59d2541..601d6f0 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -104,7 +104,7 @@
@overrideInOperand
def regId(self):
return f'(({self.reg_spec}) ==
gem5::ArmISA::int_reg::Zero) ? ' \
- f'RegId() : RegId({self.reg_class}, {self.reg_spec})'
+ f'RegId() : {self.reg_class}[{self.reg_spec}]'
def __init__(self, idx, ctype='uw', id=srtNormal):
super(IntRegNPC, self).__init__(ctype, idx, 'IsInteger', id)
@@ -168,7 +168,7 @@
@overrideInOperand
def regId(self):
return f'(({self.reg_spec}) ==
gem5::ArmISA::int_reg::Zero) ? ' \
- f'RegId() : RegId({self.reg_class}, {self.reg_spec})'
+ f'RegId() : {self.reg_class}[{self.reg_spec}]'
@overrideInOperand
def makeRead(self):
return f'{self.base_name} = ' \
diff --git a/src/arch/arm/tracers/tarmac_record.cc
b/src/arch/arm/tracers/tarmac_record.cc
index ada0b89..0668562 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -158,36 +158,33 @@
const RegId& reg)
: RegEntry(tarmCtx.pc),
regValid(false),
- regClass(reg.classValue()),
- regRel(reg.index())
+ regId(reg)
{
}
void
-TarmacTracerRecord::TraceRegEntry::update(
- const TarmacContext& tarmCtx
-)
+TarmacTracerRecord::TraceRegEntry::update(const TarmacContext& tarmCtx)
{
// Fill the register entry data, according to register
// class.
- switch (regClass) {
+ switch (regId.classValue()) {
case CCRegClass:
- updateCC(tarmCtx, regRel);
+ updateCC(tarmCtx);
break;
case FloatRegClass:
- updateFloat(tarmCtx, regRel);
+ updateFloat(tarmCtx);
break;
case IntRegClass:
- updateInt(tarmCtx, regRel);
+ updateInt(tarmCtx);
break;
case MiscRegClass:
- updateMisc(tarmCtx, regRel);
+ updateMisc(tarmCtx);
break;
case VecRegClass:
- updateVec(tarmCtx, regRel);
+ updateVec(tarmCtx);
break;
case VecPredRegClass:
- updatePred(tarmCtx, regRel);
+ updatePred(tarmCtx);
break;
default:
// If unsupported format, do nothing: non updating
@@ -197,21 +194,18 @@
}
void
-TarmacTracerRecord::TraceRegEntry::updateMisc(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecord::TraceRegEntry::updateMisc(const TarmacContext& tarmCtx)
{
auto thread = tarmCtx.thread;
regValid = true;
- regName = miscRegName[regRelIdx];
- values[Lo] = thread->readMiscRegNoEffect(regRelIdx);
+ regName = miscRegName[regId.index()];
+ values[Lo] = thread->readMiscRegNoEffect(regId.index());
// If it is the CPSR:
// update the value of the CPSR register and add
// the CC flags on top of the value
- if (regRelIdx == MISCREG_CPSR) {
+ if (regId.index() == MISCREG_CPSR) {
CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
cpsr.nz = thread->getReg(cc_reg::Nz);
cpsr.c = thread->getReg(cc_reg::C);
@@ -224,34 +218,25 @@
}
void
-TarmacTracerRecord::TraceRegEntry::updateCC(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecord::TraceRegEntry::updateCC(const TarmacContext& tarmCtx)
{
auto thread = tarmCtx.thread;
regValid = true;
- regName = cc_reg::RegName[regRelIdx];
- values[Lo] = thread->getReg(ccRegClass[regRelIdx]);
+ regName = cc_reg::RegName[regId.index()];
+ values[Lo] = thread->getReg(regId);
}
void
-TarmacTracerRecord::TraceRegEntry::updateFloat(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecord::TraceRegEntry::updateFloat(const TarmacContext&
tarmCtx)
{
regValid = true;
- regName = "f" + std::to_string(regRelIdx);
+ regName = "f" + std::to_string(regId.index());
panic("ARM doesn't support float registers.");
}
void
-TarmacTracerRecord::TraceRegEntry::updateInt(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecord::TraceRegEntry::updateInt(const TarmacContext& tarmCtx)
{
auto thread = tarmCtx.thread;
@@ -267,7 +252,7 @@
}
regValid = true;
- switch (regRelIdx) {
+ switch (regId.index()) {
case int_reg::Pc:
regName = "pc";
break;
@@ -281,10 +266,10 @@
regName = "lr" + reg_suffix;
break;
default:
- regName = "r" + std::to_string(regRelIdx);
+ regName = "r" + std::to_string(regId.index());
break;
}
- values[Lo] = thread->getReg(intRegClass[regRelIdx]);
+ values[Lo] = thread->getReg(regId);
}
void
diff --git a/src/arch/arm/tracers/tarmac_record.hh
b/src/arch/arm/tracers/tarmac_record.hh
index 87514b48..42d539c 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -140,31 +140,18 @@
protected:
/** Register update functions. */
- virtual void
- updateMisc(const TarmacContext& tarmCtx, RegIndex regRelIdx);
-
- virtual void
- updateCC(const TarmacContext& tarmCtx, RegIndex regRelIdx);
-
- virtual void
- updateFloat(const TarmacContext& tarmCtx, RegIndex regRelIdx);
-
- virtual void
- updateInt(const TarmacContext& tarmCtx, RegIndex regRelIdx);
-
- virtual void
- updateVec(const TarmacContext& tarmCtx, RegIndex regRelIdx) {};
-
- virtual void
- updatePred(const TarmacContext& tarmCtx, RegIndex regRelIdx) {};
+ virtual void updateMisc(const TarmacContext& tarmCtx);
+ virtual void updateCC(const TarmacContext& tarmCtx);
+ virtual void updateFloat(const TarmacContext& tarmCtx);
+ virtual void updateInt(const TarmacContext& tarmCtx);
+ virtual void updateVec(const TarmacContext& tarmCtx) {};
+ virtual void updatePred(const TarmacContext& tarmCtx) {};
public:
/** True if register entry is valid */
bool regValid;
- /** Register class */
- RegClassType regClass;
- /** Register arch number */
- RegIndex regRel;
+ /** Register ID */
+ RegId regId;
/** Register name to be printed */
std::string regName;
};
@@ -229,7 +216,9 @@
// Find all CC Entries and move them at the end of the queue
auto it = std::remove_if(
queue.begin(), queue.end(),
- [] (RegPtr& reg) ->bool { return (reg->regClass ==
CCRegClass); }
+ [] (RegPtr& reg) ->bool {
+ return (reg->regId.classValue() == CCRegClass);
+ }
);
if (it != queue.end()) {
@@ -238,8 +227,8 @@
auto is_cpsr = [] (RegPtr& reg) ->bool
{
- return (reg->regClass == MiscRegClass) &&
- (reg->regRel == ArmISA::MISCREG_CPSR);
+ return (reg->regId.classValue()== MiscRegClass) &&
+ (reg->regId.index() == ArmISA::MISCREG_CPSR);
};
// Looking for the presence of a CPSR register entry.
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc
b/src/arch/arm/tracers/tarmac_record_v8.cc
index 3c4a152..c025969 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -90,22 +90,19 @@
}
void
-TarmacTracerRecordV8::TraceRegEntryV8::updateInt(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecordV8::TraceRegEntryV8::updateInt(const TarmacContext&
tarmCtx)
{
// Do not trace pseudo register accesses: invalid
// register entry.
- if (regRelIdx > int_reg::NumArchRegs) {
+ if (regId.index() > int_reg::NumArchRegs) {
regValid = false;
return;
}
- TraceRegEntry::updateInt(tarmCtx, regRelIdx);
+ TraceRegEntry::updateInt(tarmCtx);
- if ((regRelIdx != int_reg::Pc) || (regRelIdx != StackPointerReg) ||
- (regRelIdx != FramePointerReg) || (regRelIdx != ReturnAddressReg))
{
+ if ((regId != int_reg::Pc) || (regId != StackPointerReg) ||
+ (regId != FramePointerReg) || (regId != ReturnAddressReg)) {
const auto* arm_inst = static_cast<const ArmStaticInst*>(
tarmCtx.staticInst.get()
@@ -113,33 +110,27 @@
regWidth = (arm_inst->getIntWidth());
if (regWidth == 32) {
- regName = "W" + std::to_string(regRelIdx);
+ regName = "W" + std::to_string(regId.index());
} else {
- regName = "X" + std::to_string(regRelIdx);
+ regName = "X" + std::to_string(regId.index());
}
}
}
void
-TarmacTracerRecordV8::TraceRegEntryV8::updateMisc(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecordV8::TraceRegEntryV8::updateMisc(const TarmacContext&
tarmCtx)
{
- TraceRegEntry::updateMisc(tarmCtx, regRelIdx);
+ TraceRegEntry::updateMisc(tarmCtx);
// System registers are 32bit wide
regWidth = 32;
}
void
-TarmacTracerRecordV8::TraceRegEntryV8::updateVec(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecordV8::TraceRegEntryV8::updateVec(const TarmacContext&
tarmCtx)
{
auto thread = tarmCtx.thread;
ArmISA::VecRegContainer vec_container;
- thread->getReg(RegId(regClass, regRelIdx), &vec_container);
+ thread->getReg(regId, &vec_container);
auto vv = vec_container.as<VecElem>();
regWidth = ArmStaticInst::getCurSveVecLenInBits(thread);
@@ -153,18 +144,15 @@
}
regValid = true;
- regName = "Z" + std::to_string(regRelIdx);
+ regName = "Z" + std::to_string(regId.index());
}
void
-TarmacTracerRecordV8::TraceRegEntryV8::updatePred(
- const TarmacContext& tarmCtx,
- RegIndex regRelIdx
-)
+TarmacTracerRecordV8::TraceRegEntryV8::updatePred(const TarmacContext&
tarmCtx)
{
auto thread = tarmCtx.thread;
ArmISA::VecPredRegContainer pred_container;
- thread->getReg(RegId(regClass, regRelIdx), &pred_container);
+ thread->getReg(regId, &pred_container);
// Predicate registers are always 1/8 the size of related vector
// registers. (getCurSveVecLenInBits(thread) / 8)
@@ -181,7 +169,7 @@
}
regValid = true;
- regName = "P" + std::to_string(regRelIdx);
+ regName = "P" + std::to_string(regId.index());
}
void
diff --git a/src/arch/arm/tracers/tarmac_record_v8.hh
b/src/arch/arm/tracers/tarmac_record_v8.hh
index 4a65806..75e035f 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.hh
+++ b/src/arch/arm/tracers/tarmac_record_v8.hh
@@ -103,17 +103,10 @@
const std::string &prefix = "") const override;
protected:
- void updateInt(const TarmacContext& tarmCtx,
- RegIndex regRelIdx) override;
-
- void updateMisc(const TarmacContext& tarmCtx,
- RegIndex regRelIdx) override;
-
- void updateVec(const TarmacContext& tarmCtx,
- RegIndex regRelIdx) override;
-
- void updatePred(const TarmacContext& tarmCtx,
- RegIndex regRelIdx) override;
+ void updateInt(const TarmacContext& tarmCtx) override;
+ void updateMisc(const TarmacContext& tarmCtx) override;
+ void updateVec(const TarmacContext& tarmCtx) override;
+ void updatePred(const TarmacContext& tarmCtx) override;
/**
* Returning a string which contains the formatted
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index ea4eb93..441fc9d 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -1347,7 +1347,7 @@
for (int ri = 0; ri < NumVecRegs; ri++) {
VecRegContainer reg;
for (int j = 0; j < NumVecElemPerVecReg; j++, ei++) {
- RegId elem_id(VecElemClass, ei);
+ RegId elem_id = vecElemClass[ei];
reg.as<VecElem>()[j] = tc->getReg(elem_id);
}
tc->setReg(vecRegClass[ri], ®);
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index eff8155..d7babe7 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -114,7 +114,7 @@
dst_reg_constructor = '\n\tsetDestRegIdx(_numDestRegs++, %s);'
def regId(self):
- return f'RegId({self.reg_class}, {self.reg_spec})'
+ return f'{self.reg_class}[{self.reg_spec}]'
def srcRegId(self):
return self.regId()
@@ -203,7 +203,7 @@
if self.is_dest:
c_dest = self.dst_reg_constructor % self.destRegId()
- c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
+ c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}.type()]++;'
return c_src + c_dest
@@ -244,25 +244,25 @@
class IntRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(IntRegOperandDesc, self).__init__(
- 'IntRegClass', 'Reg', *args, **kwargs)
+ 'intRegClass', 'Reg', *args, **kwargs)
class FloatRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(FloatRegOperandDesc, self).__init__(
- 'FloatRegClass', 'Reg', *args, **kwargs)
+ 'floatRegClass', 'Reg', *args, **kwargs)
class CCRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(CCRegOperandDesc, self).__init__(
- 'CCRegClass', 'Reg', *args, **kwargs)
+ 'ccRegClass', 'Reg', *args, **kwargs)
class VecElemOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(VecElemOperandDesc, self).__init__(
- 'VecElemClass', 'Reg', *args, **kwargs)
+ 'vecElemClass', 'Reg', *args, **kwargs)
class VecRegOperand(BaseRegOperand):
- reg_class = 'VecRegClass'
+ reg_class = 'vecRegClass'
def __init__(self, parser, full_name, ext, is_src, is_dest):
Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
@@ -374,10 +374,10 @@
class VecRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(VecRegOperandDesc, self).__init__(
- 'VecRegClass', 'VecReg', *args, **kwargs)
+ 'vecRegClass', 'VecReg', *args, **kwargs)
class VecPredRegOperand(BaseRegOperand):
- reg_class = 'VecPredRegClass'
+ reg_class = 'vecPredRegClass'
def makeDecl(self):
return ''
@@ -420,10 +420,10 @@
class VecPredRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(VecPredRegOperandDesc, self).__init__(
- 'VecPredRegClass', 'VecPredReg', *args, **kwargs)
+ 'vecPredRegClass', 'VecPredReg', *args, **kwargs)
class ControlRegOperand(Operand):
- reg_class = 'MiscRegClass'
+ reg_class = 'miscRegClass'
def isReg(self):
return 1
@@ -467,7 +467,7 @@
class ControlRegOperandDesc(RegOperandDesc):
def __init__(self, *args, **kwargs):
super(ControlRegOperandDesc, self).__init__(
- 'MiscRegClass', 'ControlReg', *args, **kwargs)
+ 'miscRegClass', 'ControlReg', *args, **kwargs)
class MemOperand(Operand):
def isMem(self):
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index bd52b18..53df90e 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -44,7 +44,7 @@
@overrideInOperand
def regId(self):
return f'(({self.reg_spec}) == 0) ? RegId() : ' \
- f'RegId({self.reg_class}, {self.reg_spec})'
+ f'{self.reg_class}[{self.reg_spec}]'
}};
def operands {{
diff --git a/src/arch/power/isa/includes.isa
b/src/arch/power/isa/includes.isa
index e9b950b..99ad9d1 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -55,6 +55,7 @@
#include "arch/power/decoder.hh"
#include "arch/power/faults.hh"
+#include "arch/power/regs/float.hh"
#include "arch/power/regs/int.hh"
#include "base/loader/symtab.hh"
#include "base/cprintf.hh"
diff --git a/src/arch/riscv/isa/operands.isa
b/src/arch/riscv/isa/operands.isa
index 4f0c3ed..72d8f81 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -46,7 +46,7 @@
@overrideInOperand
def regId(self):
return f'(({self.reg_spec}) == 0) ? RegId() : ' \
- f'RegId({self.reg_class}, {self.reg_spec})'
+ f'{self.reg_class}[{self.reg_spec}]'
}};
def operands {{
diff --git a/src/arch/sparc/isa/includes.isa
b/src/arch/sparc/isa/includes.isa
index c561056..624679d 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -60,6 +60,7 @@
#include <algorithm>
#include "arch/sparc/decoder.hh"
+#include "arch/sparc/regs/float.hh"
#include "base/cprintf.hh"
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
diff --git a/src/arch/sparc/isa/operands.isa
b/src/arch/sparc/isa/operands.isa
index 4e05563..ba3ce3a 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -70,7 +70,7 @@
@overrideInOperand
def regId(self):
return f'(({self.reg_spec}) == 0) ? RegId() : ' \
- f'RegId({self.reg_class}, {self.reg_spec})'
+ f'{self.reg_class}[{self.reg_spec}]'
}};
def operands {{
diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa
index 500d1db..ad220c5 100644
--- a/src/arch/x86/isa/includes.isa
+++ b/src/arch/x86/isa/includes.isa
@@ -73,12 +73,7 @@
#include "sim/faults.hh"
using namespace gem5;
-using X86ISA::GpRegIndex;
-using X86ISA::FpRegIndex;
-using X86ISA::CtrlRegIndex;
-using X86ISA::CrRegIndex;
-using X86ISA::DbgRegIndex;
-using X86ISA::SegRegIndex;
+using namespace X86ISA;
}};
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 6b58dcb..6cb1c6b 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -58,7 +58,7 @@
@overrideInOperand
def regId(self):
return f'(({self.reg_spec}) == gem5::X86ISA::int_reg::T0) ? ' \
- f'RegId() : RegId({self.reg_class}, {self.reg_spec})'
+ f'RegId() : {self.reg_class}[{self.reg_spec}]'
def __init__(self, idx, id, data_size='dataSize', *args, **kwargs):
super(IntReg, self).__init__(
'uqw', idx, 'IsInteger', id, *args, **kwargs)
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index 83a78e2..37fd1e3 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -64,6 +64,7 @@
DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
DebugFlag('Fetch')
DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)')
+DebugFlag('InvalidReg')
DebugFlag('O3PipeView')
DebugFlag('PCEvent')
DebugFlag('Quiesce')
diff --git a/src/cpu/o3/regfile.cc b/src/cpu/o3/regfile.cc
index b557fef..a8de1f3 100644
--- a/src/cpu/o3/regfile.cc
+++ b/src/cpu/o3/regfile.cc
@@ -84,42 +84,48 @@
// The initial batch of registers are the integer ones
for (phys_reg = 0; phys_reg < numPhysicalIntRegs; phys_reg++) {
- intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
+ intRegIds.emplace_back(*reg_classes.at(IntRegClass),
+ phys_reg, flat_reg_idx++);
}
// The next batch of the registers are the floating-point physical
// registers; put them onto the floating-point free list.
for (phys_reg = 0; phys_reg < numPhysicalFloatRegs; phys_reg++) {
- floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++);
+ floatRegIds.emplace_back(*reg_classes.at(FloatRegClass),
+ phys_reg, flat_reg_idx++);
}
// The next batch of the registers are the vector physical
// registers; put them onto the vector free list.
for (phys_reg = 0; phys_reg < numPhysicalVecRegs; phys_reg++) {
- vecRegIds.emplace_back(VecRegClass, phys_reg, flat_reg_idx++);
+ vecRegIds.emplace_back(*reg_classes.at(VecRegClass), phys_reg,
+ flat_reg_idx++);
}
// The next batch of the registers are the vector element physical
// registers; put them onto the vector free list.
for (phys_reg = 0; phys_reg < numPhysicalVecElemRegs; phys_reg++) {
- vecElemIds.emplace_back(VecElemClass, phys_reg, flat_reg_idx++);
+ vecElemIds.emplace_back(*reg_classes.at(VecElemClass), phys_reg,
+ flat_reg_idx++);
}
// The next batch of the registers are the predicate physical
// registers; put them onto the predicate free list.
for (phys_reg = 0; phys_reg < numPhysicalVecPredRegs; phys_reg++) {
- vecPredRegIds.emplace_back(VecPredRegClass, phys_reg,
flat_reg_idx++);
+ vecPredRegIds.emplace_back(*reg_classes.at(VecPredRegClass),
phys_reg,
+ flat_reg_idx++);
}
// The rest of the registers are the condition-code physical
// registers; put them onto the condition-code free list.
for (phys_reg = 0; phys_reg < numPhysicalCCRegs; phys_reg++) {
- ccRegIds.emplace_back(CCRegClass, phys_reg, flat_reg_idx++);
+ ccRegIds.emplace_back(*reg_classes.at(CCRegClass), phys_reg,
+ flat_reg_idx++);
}
// Misc regs have a fixed mapping but still need PhysRegIds.
for (phys_reg = 0; phys_reg < reg_classes.at(MiscRegClass)->size();
phys_reg++) {
- miscRegIds.emplace_back(MiscRegClass, phys_reg, 0);
+ miscRegIds.emplace_back(*reg_classes.at(MiscRegClass), phys_reg,
0);
}
}
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index 26e9e60..7be8988 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -51,6 +51,7 @@
#include "base/debug.hh"
#include "base/intmath.hh"
#include "base/types.hh"
+#include "debug/InvalidReg.hh"
namespace gem5
{
@@ -132,6 +133,9 @@
inline constexpr RegId operator[](RegIndex idx) const;
};
+inline constexpr RegClass
+ invalidRegClass(InvalidRegClass, 0, debug::InvalidReg);
+
/** Register ID: describe an architectural register with its class and
index.
* This structure is used instead of just the register index to
disambiguate
* between different classes of registers. For example, a integer register
with
@@ -141,7 +145,7 @@
{
protected:
static const char* regClassStrings[];
- RegClassType regClass;
+ const RegClass *_regClass = nullptr;
RegIndex regIdx;
int numPinnedWrites;
@@ -149,10 +153,10 @@
friend class RegClassIterator;
public:
- constexpr RegId() : RegId(InvalidRegClass, 0) {}
+ constexpr RegId() : RegId(invalidRegClass, 0) {}
- explicit constexpr RegId(RegClassType reg_class, RegIndex reg_idx)
- : regClass(reg_class), regIdx(reg_idx), numPinnedWrites(0)
+ explicit constexpr RegId(const RegClass ®_class, RegIndex reg_idx)
+ : _regClass(®_class), regIdx(reg_idx), numPinnedWrites(0)
{}
constexpr operator RegIndex() const
@@ -163,7 +167,7 @@
constexpr bool
operator==(const RegId& that) const
{
- return regClass == that.classValue() && regIdx == that.index();
+ return classValue() == that.classValue() && regIdx == that.index();
}
constexpr bool
@@ -178,8 +182,8 @@
constexpr bool
operator<(const RegId& that) const
{
- return regClass < that.classValue() ||
- (regClass == that.classValue() && (regIdx < that.index()));
+ return classValue() < that.classValue() ||
+ (classValue() == that.classValue() && (regIdx < that.index()));
}
/**
@@ -188,14 +192,14 @@
constexpr bool
isRenameable() const
{
- return regClass != MiscRegClass && regClass != InvalidRegClass;
+ return classValue() != MiscRegClass && classValue() !=
InvalidRegClass;
}
/** @return true if it is of the specified class. */
constexpr bool
is(RegClassType reg_class) const
{
- return regClass == reg_class;
+ return _regClass->type() == reg_class;
}
/** Index accessors */
@@ -203,12 +207,13 @@
constexpr RegIndex index() const { return regIdx; }
/** Class accessor */
- constexpr RegClassType classValue() const { return regClass; }
+ constexpr const RegClass ®Class() const { return *_regClass; }
+ constexpr RegClassType classValue() const { return _regClass->type(); }
/** Return a const char* with the register class name. */
constexpr const char*
className() const
{
- return regClassStrings[regClass];
+ return regClassStrings[classValue()];
}
int getNumPinnedWrites() const { return numPinnedWrites; }
@@ -228,7 +233,7 @@
RegId id;
RegClassIterator(const RegClass ®_class, RegIndex idx=0) :
- regClass(reg_class), id(reg_class.type(), idx)
+ regClass(reg_class), id(reg_class, idx)
{}
friend class RegClass;
@@ -286,7 +291,7 @@
constexpr RegId
RegClass::operator[](RegIndex idx) const
{
- return RegId(type(), idx);
+ return RegId(*this, idx);
}
template <typename ValueType>
@@ -331,14 +336,14 @@
bool pinned;
public:
- explicit PhysRegId() : RegId(InvalidRegClass, -1), flatIdx(-1),
+ explicit PhysRegId() : RegId(invalidRegClass, -1), flatIdx(-1),
numPinnedWritesToComplete(0)
{}
/** Scalar PhysRegId constructor. */
- explicit PhysRegId(RegClassType _regClass, RegIndex _regIdx,
+ explicit PhysRegId(const RegClass ®_class, RegIndex _regIdx,
RegIndex _flatIdx)
- : RegId(_regClass, _regIdx), flatIdx(_flatIdx),
+ : RegId(reg_class, _regIdx), flatIdx(_flatIdx),
numPinnedWritesToComplete(0), pinned(false)
{}
@@ -432,7 +437,7 @@
{
// Extract unique integral values for the effective fields of a
RegId.
const size_t index = static_cast<size_t>(reg_id.index());
- const size_t class_num = static_cast<size_t>(reg_id.regClass);
+ const size_t class_num = static_cast<size_t>(reg_id.classValue());
const size_t shifted_class_num =
class_num << (sizeof(gem5::RegIndex) << 3);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49786
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4cfff2069d63f3c1c3fb0fea5dee3baf357bd478
Gerrit-Change-Number: 49786
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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