Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50254 )
Change subject: arch,cpu,sim: Store registers in InstRecord with InstResult.
......................................................................
arch,cpu,sim: Store registers in InstRecord with InstResult.
The InstResult knows how to print registers without having to know about
their actual types. This lets us get rid of the final use of
TheISA::VecRegContainer and TheISA::VecPredRegContainer.
Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
---
M src/arch/arm/insts/tme64ruby.cc
M src/arch/arm/isa/operands.isa
M src/arch/isa_parser/operand_types.py
M src/arch/mips/isa/formats/fp.isa
M src/arch/power/isa/includes.isa
M src/arch/sparc/isa/includes.isa
M src/cpu/exetrace.cc
M src/sim/insttracer.hh
8 files changed, 54 insertions(+), 63 deletions(-)
diff --git a/src/arch/arm/insts/tme64ruby.cc
b/src/arch/arm/insts/tme64ruby.cc
index 1150ebb..42a8a56 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -127,7 +127,7 @@
uint64_t final_val = Dest64;
- if (traceData) { traceData->setData(final_val); }
+ if (traceData) { traceData->setData(intRegClass, final_val); }
}
return fault;
@@ -157,7 +157,7 @@
if (fault == NoFault) {
uint64_t final_val = Dest64;
xc->setRegOperand(this, 0, Dest64 & mask(intWidth));
- if (traceData) { traceData->setData(final_val); }
+ if (traceData) { traceData->setData(intRegClass, final_val); }
}
return fault;
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 601d6f0..95ab1d5 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -122,7 +122,7 @@
else
xc->setRegOperand(this, {self.dest_reg_idx},
{self.base_name});
if (traceData)
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
'''
class PIntReg(IntReg):
@@ -145,7 +145,7 @@
else
xc->setRegOperand(this, {self.dest_reg_idx},
{self.base_name});
if (traceData)
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
'''
class IntRegAIWPC(IntReg):
@@ -161,7 +161,7 @@
xc->setRegOperand(this, {self.dest_reg_idx},
{self.base_name});
{"}"}
if (traceData)
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
'''
class IntReg64(IntRegOp):
@@ -180,7 +180,7 @@
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(intWidth));
if (traceData)
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
'''
def __init__(self, idx, id=srtNormal):
super(IntReg64, self).__init__('ud', idx, 'IsInteger', id)
@@ -197,7 +197,7 @@
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(aarch64 ? 64 : 32));
if (traceData)
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
'''
class IntRegW64(IntReg64):
@@ -212,7 +212,7 @@
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(32));
if (traceData)
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
'''
class CCReg(CCRegOp):
@@ -234,7 +234,7 @@
xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()),
{self.base_name});
if (traceData)
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
'''
def __init__(self, idx, id=srtNormal, ctype='uw'):
super(CntrlNsBankedReg, self).__init__(idx, id, ctype,
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index d7babe7..d684219 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -232,7 +232,7 @@
RegVal final_val = {reg_val};
xc->setRegOperand(this, {self.dest_reg_idx}, final_val);
if (traceData) {{
- traceData->setData(final_val);
+ traceData->setData({self.reg_class}, final_val);
}}
}}'''
@@ -361,7 +361,7 @@
def makeWrite(self):
wb = f'''
if (traceData) {{
- traceData->setData(tmp_d{self.dest_reg_idx});
+ traceData->setData({self.reg_class},
&tmp_d{self.dest_reg_idx});
}}
'''
return wb
@@ -407,7 +407,7 @@
def makeWrite(self):
wb = f'''
if (traceData) {{
- traceData->setData(tmp_d{self.dest_reg_idx});
+ traceData->setData({self.reg_class},
&tmp_d{self.dest_reg_idx});
}}
'''
return wb
@@ -458,7 +458,7 @@
f'{self.dest_reg_idx}, {self.base_name});\n'
wb += f'''
if (traceData) {{
- traceData->setData({self.base_name});
+ traceData->setData({self.reg_class}, {self.base_name});
}}
'''
diff --git a/src/arch/mips/isa/formats/fp.isa
b/src/arch/mips/isa/formats/fp.isa
index 93786fd..877a2b1 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -109,7 +109,7 @@
if (isNan(&src_bits, 32) ) {
mips_nan = MIPS32_QNAN;
xc->setRegOperand(inst, 0, mips_nan);
- if (traceData) { traceData->setData(mips_nan); }
+ if (traceData) { traceData->setData(floatRegClass,
mips_nan); }
return true;
}
}
@@ -139,7 +139,7 @@
//Write FCSR from FloatRegFile
cpu->tcBase()->setReg(float_reg::Fcsr, new_fcsr);
- if (traceData) { traceData->setData(mips_nan); }
+ if (traceData) { traceData->setData(floatRegClass, mips_nan); }
return true;
}
diff --git a/src/arch/power/isa/includes.isa
b/src/arch/power/isa/includes.isa
index 99ad9d1..696497b 100644
--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -70,6 +70,7 @@
#include "arch/generic/memhelpers.hh"
#include "arch/power/faults.hh"
+#include "arch/power/regs/float.hh"
#include "arch/power/regs/int.hh"
#include "arch/power/regs/misc.hh"
#include "base/condcodes.hh"
diff --git a/src/arch/sparc/isa/includes.isa
b/src/arch/sparc/isa/includes.isa
index 624679d..b321bc0 100644
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -78,6 +78,7 @@
#include "arch/generic/memhelpers.hh"
#include "arch/sparc/asi.hh"
#include "arch/sparc/pseudo_inst_abi.hh"
+#include "arch/sparc/regs/float.hh"
#include "base/fenv.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 6c129b9..44f55b7 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -115,18 +115,11 @@
outs << "Predicated False";
}
- if (debug::ExecResult && data_status != DataInvalid) {
- switch (data_status) {
- case DataVec:
- ccprintf(outs, " D=%s", *data.as_vec);
- break;
- case DataVecPred:
- ccprintf(outs, " D=%s", *data.as_pred);
- break;
- default:
- ccprintf(outs, " D=%#018x", data.as_int);
- break;
- }
+ if (debug::ExecResult && dataStatus != DataInvalid) {
+ if (dataStatus == DataReg)
+ ccprintf(outs, " D=%s", data.asReg.asString());
+ else
+ ccprintf(outs, " D=%#018x", data.asInt);
}
if (debug::ExecEffAddr && getMemValid())
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 6bb5bd3..0cf1b3b 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -43,6 +43,7 @@
#include "arch/vecregs.hh"
#include "base/types.hh"
+#include "cpu/inst_res.hh"
#include "cpu/inst_seq.hh"
#include "cpu/static_inst.hh"
#include "sim/sim_object.hh"
@@ -93,12 +94,13 @@
* @TODO fix this and record all destintations that an instruction
writes
* @see data_status
*/
- union
+ union Data
{
- uint64_t as_int;
- double as_double;
- TheISA::VecRegContainer* as_vec;
- TheISA::VecPredRegContainer* as_pred;
+ ~Data() {}
+ Data() {}
+ uint64_t asInt = 0;
+ double asDouble;
+ InstResult asReg;
} data;
/** @defgroup fetch_seq
@@ -124,9 +126,8 @@
DataInt32 = 4,
DataInt64 = 8,
DataDouble = 3,
- DataVec = 5,
- DataVecPred = 6
- } data_status = DataInvalid;
+ DataReg = 5
+ } dataStatus = DataInvalid;
/** @ingroup memory
* Are the memory fields in the record valid?
@@ -163,13 +164,8 @@
virtual ~InstRecord()
{
- if (data_status == DataVec) {
- assert(data.as_vec);
- delete data.as_vec;
- } else if (data_status == DataVecPred) {
- assert(data.as_pred);
- delete data.as_pred;
- }
+ if (dataStatus == DataReg)
+ data.asReg.~InstResult();
}
void setWhen(Tick new_when) { when = new_when; }
@@ -186,8 +182,8 @@
void
setData(std::array<T, N> d)
{
- data.as_int = d[0];
- data_status = (DataStatus)sizeof(T);
+ data.asInt = d[0];
+ dataStatus = (DataStatus)sizeof(T);
static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
"Type T has an unrecognized size.");
@@ -196,26 +192,26 @@
void
setData(uint64_t d)
{
- data.as_int = d;
- data_status = DataInt64;
+ data.asInt = d;
+ dataStatus = DataInt64;
}
void
setData(uint32_t d)
{
- data.as_int = d;
- data_status = DataInt32;
+ data.asInt = d;
+ dataStatus = DataInt32;
}
void
setData(uint16_t d)
{
- data.as_int = d;
- data_status = DataInt16;
+ data.asInt = d;
+ dataStatus = DataInt16;
}
void
setData(uint8_t d)
{
- data.as_int = d;
- data_status = DataInt8;
+ data.asInt = d;
+ dataStatus = DataInt8;
}
void setData(int64_t d) { setData((uint64_t)d); }
@@ -226,22 +222,22 @@
void
setData(double d)
{
- data.as_double = d;
- data_status = DataDouble;
+ data.asDouble = d;
+ dataStatus = DataDouble;
}
void
- setData(TheISA::VecRegContainer& d)
+ setData(const RegClass ®_class, RegVal val)
{
- data.as_vec = new TheISA::VecRegContainer(d);
- data_status = DataVec;
+ new(&data.asReg) InstResult(reg_class, val);
+ dataStatus = DataReg;
}
void
- setData(TheISA::VecPredRegContainer& d)
+ setData(const RegClass ®_class, const void *val)
{
- data.as_pred = new TheISA::VecPredRegContainer(d);
- data_status = DataVecPred;
+ new(&data.asReg) InstResult(reg_class, val);
+ dataStatus = DataReg;
}
void
@@ -276,9 +272,9 @@
unsigned getFlags() const { return flags; }
bool getMemValid() const { return mem_valid; }
- uint64_t getIntData() const { return data.as_int; }
- double getFloatData() const { return data.as_double; }
- int getDataStatus() const { return data_status; }
+ uint64_t getIntData() const { return data.asInt; }
+ double getFloatData() const { return data.asDouble; }
+ int getDataStatus() const { return dataStatus; }
InstSeqNum getFetchSeq() const { return fetch_seq; }
bool getFetchSeqValid() const { return fetch_seq_valid; }
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50254
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
Gerrit-Change-Number: 50254
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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