Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/50343 )
Change subject: sim: Encapsulate MemPool related System stuff in a MemPools
class.
......................................................................
sim: Encapsulate MemPool related System stuff in a MemPools class.
Also add a const version of the getPhysMem accessor so it can be used
with a const System class.
Change-Id: Ieccd0bd4c2c8fe69820eb1a0b0c835722334630d
---
D src/python/pybind11/core.hh
M src/sim/mem_pool.cc
M src/sim/mem_pool.hh
M src/sim/system.cc
M src/sim/system.hh
5 files changed, 115 insertions(+), 93 deletions(-)
diff --git a/src/python/pybind11/core.hh b/src/python/pybind11/core.hh
deleted file mode 100644
index d90854f..0000000
--- a/src/python/pybind11/core.hh
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2017 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __PYTHON_PYBIND11_CORE_HH__
-#define __PYTHON_PYBIND11_CORE_HH__
-
-#include "pybind11/cast.h"
-#include "pybind11/stl_bind.h"
-
-#include <vector>
-
-#include "base/addr_range.hh"
-
-PYBIND11_MAKE_OPAQUE(std::vector<gem5::AddrRange>);
-
-#endif // __PYTHON_PYBIND11_CORE_HH__
diff --git a/src/sim/mem_pool.cc b/src/sim/mem_pool.cc
index ad68a6b..947636c 100644
--- a/src/sim/mem_pool.cc
+++ b/src/sim/mem_pool.cc
@@ -33,7 +33,11 @@
#include "sim/mem_pool.hh"
+#include <cassert>
+
+#include "base/addr_range.hh"
#include "base/logging.hh"
+#include "sim/system.hh"
namespace gem5
{
@@ -126,4 +130,70 @@
paramIn(cp, "total_pages", _totalPages);
}
+void
+MemPools::populate(const System &sys)
+{
+ AddrRangeList memories = sys.getPhysMem().getConfAddrRanges();
+ const auto &m5op_range = sys.m5opRange();
+
+ assert(!memories.empty());
+ for (const auto &mem : memories) {
+ assert(!mem.interleaved());
+ if (m5op_range.valid()) {
+ // Make sure the m5op range is not included.
+ for (const auto &range: mem.exclude({m5op_range}))
+ pools.emplace_back(pageShift, range.start(), range.end());
+ } else {
+ pools.emplace_back(pageShift, mem.start(), mem.end());
+ }
+ }
+
+ /*
+ * Set freePage to what it was before Gabe Black's page table changes
+ * so allocations don't trample the page table entries.
+ */
+ pools[0].setFreePage(pools[0].freePage() + 70);
+}
+
+Addr
+MemPools::allocPhysPages(int npages, int pool_id)
+{
+ return pools[pool_id].allocate(npages);
+}
+
+Addr
+MemPools::memSize(int pool_id) const
+{
+ return pools[pool_id].totalBytes();
+}
+
+Addr
+MemPools::freeMemSize(int pool_id) const
+{
+ return pools[pool_id].freeBytes();
+}
+
+void
+MemPools::serialize(CheckpointOut &cp) const
+{
+ int num_pools = pools.size();
+ SERIALIZE_SCALAR(num_pools);
+
+ for (int i = 0; i < num_pools; i++)
+ pools[i].serializeSection(cp, csprintf("pool%d", i));
+}
+
+void
+MemPools::unserialize(CheckpointIn &cp)
+{
+ int num_pools = 0;
+ UNSERIALIZE_SCALAR(num_pools);
+
+ for (int i = 0; i < num_pools; i++) {
+ MemPool pool;
+ pool.unserializeSection(cp, csprintf("pool%d", i));
+ pools.push_back(pool);
+ }
+}
+
} // namespace gem5
diff --git a/src/sim/mem_pool.hh b/src/sim/mem_pool.hh
index 2402d74..7cc3571 100644
--- a/src/sim/mem_pool.hh
+++ b/src/sim/mem_pool.hh
@@ -34,6 +34,8 @@
#ifndef __MEM_POOL_HH__
#define __MEM_POOL_HH__
+#include <vector>
+
#include "base/types.hh"
#include "sim/serialize.hh"
@@ -54,9 +56,11 @@
/** The size of the pool, in number of pages. */
Counter _totalPages = 0;
- public:
MemPool() {}
+ friend class MemPools;
+
+ public:
MemPool(Addr page_shift, Addr ptr, Addr limit);
Counter freePage() const;
@@ -77,6 +81,32 @@
void unserialize(CheckpointIn &cp) override;
};
+class MemPools : public Serializable
+{
+ private:
+ Addr pageShift;
+
+ std::vector<MemPool> pools;
+
+ public:
+ MemPools(Addr page_shift) : pageShift(page_shift) {}
+
+ void populate(const System &sys);
+
+ /// Allocate npages contiguous unused physical pages.
+ /// @return Starting address of first page
+ Addr allocPhysPages(int npages, int pool_id=0);
+
+ /** Amount of physical memory that exists in a pool. */
+ Addr memSize(int pool_id=0) const;
+
+ /** Amount of physical memory that is still free in a pool. */
+ Addr freeMemSize(int pool_id=0) const;
+
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+};
+
} // namespace gem5
#endif // __MEM_POOL_HH__
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 5196c71..8777fc4 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -199,6 +199,7 @@
System::System(const Params &p)
: SimObject(p), _systemPort("system_port", this),
multiThread(p.multi_thread),
+ memPools(getPageShift()),
init_param(p.init_param),
physProxy(_systemPort, p.cache_line_size),
workload(p.workload),
@@ -221,6 +222,9 @@
if (workload)
workload->setSystem(this);
+ if (!FullSystem)
+ memPools.populate(*this);
+
// add self to global system list
systemList.push_back(this);
@@ -230,28 +234,6 @@
}
#endif
- if (!FullSystem) {
- AddrRangeList memories = physmem.getConfAddrRanges();
- assert(!memories.empty());
- for (const auto &mem : memories) {
- assert(!mem.interleaved());
- if (_m5opRange.valid()) {
- // Make sure the m5op range is not included.
- for (const auto &range: mem.exclude({_m5opRange}))
- memPools.emplace_back(getPageShift(),
- range.start(), range.end());
- } else {
- memPools.emplace_back(getPageShift(), mem.start(),
mem.end());
- }
- }
-
- /*
- * Set freePage to what it was before Gabe Black's page table
changes
- * so allocations don't trample the page table entries.
- */
- memPools[0].setFreePage(memPools[0].freePage() + 70);
- }
-
// check if the cache line size is a value known to work
if (_cacheLineSize != 16 && _cacheLineSize != 32 &&
_cacheLineSize != 64 && _cacheLineSize != 128) {
@@ -361,24 +343,24 @@
}
Addr
-System::allocPhysPages(int npages, int poolID)
+System::allocPhysPages(int npages, int pool_id)
{
assert(!FullSystem);
- return memPools[poolID].allocate(npages);
+ return memPools.allocPhysPages(npages, pool_id);
}
Addr
-System::memSize(int poolID) const
+System::memSize(int pool_id) const
{
assert(!FullSystem);
- return memPools[poolID].totalBytes();
+ return memPools.memSize(pool_id);
}
Addr
-System::freeMemSize(int poolID) const
+System::freeMemSize(int pool_id) const
{
assert(!FullSystem);
- return memPools[poolID].freeBytes();
+ return memPools.freeMemSize(pool_id);
}
bool
@@ -432,11 +414,7 @@
paramOut(cp, csprintf("quiesceEndTick_%d", id), when);
}
- int num_mem_pools = memPools.size();
- SERIALIZE_SCALAR(num_mem_pools);
-
- for (int i = 0; i < num_mem_pools; i++)
- memPools[i].serializeSection(cp, csprintf("memPool%d", i));
+ memPools.serializeSection(cp, "memPools");
// also serialize the memories in the system
physmem.serializeSection(cp, "physmem");
@@ -458,14 +436,7 @@
# endif
}
- int num_mem_pools = 0;
- UNSERIALIZE_SCALAR(num_mem_pools);
-
- for (int i = 0; i < num_mem_pools; i++) {
- MemPool pool;
- pool.unserializeSection(cp, csprintf("memPool%d", i));
- memPools.push_back(pool);
- }
+ memPools.unserializeSection(cp, "memPools");
// also unserialize the memories in the system
physmem.unserializeSection(cp, "physmem");
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 14d4d24..a5b7dd9 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -323,7 +323,7 @@
bool remove(PCEvent *event) override;
/** Memory allocation objects for all physical memories in the system.
*/
- std::vector<MemPool> memPools;
+ MemPools memPools;
uint64_t init_param;
@@ -346,6 +346,7 @@
/** Get a pointer to access the physical memory of the system */
memory::PhysicalMemory& getPhysMem() { return physmem; }
+ const memory::PhysicalMemory& getPhysMem() const { return physmem; }
/** Amount of physical memory that is still free */
Addr freeMemSize(int poolID = 0) const;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50343
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ieccd0bd4c2c8fe69820eb1a0b0c835722334630d
Gerrit-Change-Number: 50343
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
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