Tom Rollet has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/50730 )
Change subject: cpu-o3: replace 'stores' counter per storeQueue.size()
......................................................................
cpu-o3: replace 'stores' counter per storeQueue.size()
Change-Id: If816c1f03969665010a5bd7e993fe7f87ac4d0a3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50730
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
---
M src/cpu/o3/lsq_unit.cc
M src/cpu/o3/lsq_unit.hh
2 files changed, 28 insertions(+), 20 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index a559d58..34db032 100644
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -201,7 +201,7 @@
LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
: lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1),
- stores(0), storesToWB(0),
+ storesToWB(0),
htmStarts(0), htmStops(0),
lastRetiredHtmUid(0),
cacheBlockMask(0), stalled(false),
@@ -235,7 +235,7 @@
void
LSQUnit::resetState()
{
- stores = storesToWB = 0;
+ storesToWB = 0;
// hardware transactional memory
// nesting depth
@@ -390,7 +390,7 @@
{
// Make sure it is not full before inserting an instruction.
assert(!storeQueue.full());
- assert(stores < storeQueue.capacity());
+ assert(storeQueue.size() < storeQueue.capacity());
DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
store_inst->pcState(), storeQueue.tail(), store_inst->seqNum);
@@ -402,8 +402,6 @@
store_inst->lqIt = loadQueue.end();
storeQueue.back().set(store_inst);
-
- ++stores;
}
DynInstPtr
@@ -432,8 +430,8 @@
//SQ has an extra dummy entry to differentiate
//empty/full conditions. Subtract 1 from the free entries.
DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n",
- 1 + storeQueue.capacity(), stores);
- return storeQueue.capacity() - stores;
+ 1 + storeQueue.capacity(), storeQueue.size());
+ return storeQueue.capacity() - storeQueue.size();
}
@@ -670,7 +668,7 @@
LSQUnit::executeStore(const DynInstPtr &store_inst)
{
// Make sure that a store exists.
- assert(stores != 0);
+ assert(storeQueue.size() != 0);
int store_idx = store_inst->sqIdx;
@@ -765,7 +763,7 @@
void
LSQUnit::commitStores(InstSeqNum &youngest_inst)
{
- assert(stores == 0 || storeQueue.front().valid());
+ assert(storeQueue.size() == 0 || storeQueue.front().valid());
/* Forward iterate the store queue (age order). */
for (auto& x : storeQueue) {
@@ -940,14 +938,15 @@
inst->seqNum);
}
}
- assert(stores >= 0 && storesToWB >= 0);
+ assert(storesToWB >= 0);
}
void
LSQUnit::squash(const InstSeqNum &squashed_num)
{
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
- "(Loads:%i Stores:%i)\n", squashed_num, loadQueue.size(),
stores);
+ "(Loads:%i Stores:%i)\n", squashed_num, loadQueue.size(),
+ storeQueue.size());
while (loadQueue.size() != 0 &&
loadQueue.back().instruction()->seqNum > squashed_num) {
@@ -1023,7 +1022,7 @@
memDepViolator = NULL;
}
- while (stores != 0 &&
+ while (storeQueue.size() != 0 &&
storeQueue.back().instruction()->seqNum > squashed_num) {
// Instructions marked as can WB are already committed.
if (storeQueue.back().canWB()) {
@@ -1051,7 +1050,6 @@
// memory. This is quite ugly. @todo: Figure out the proper
// place to really handle request deletes.
storeQueue.back().clear();
- --stores;
storeQueue.pop_back();
++stats.squashedStores;
@@ -1177,7 +1175,6 @@
do {
storeQueue.front().clear();
storeQueue.pop_front();
- --stores;
} while (storeQueue.front().completed() &&
!storeQueue.empty());
@@ -1287,7 +1284,7 @@
}
cprintf("\n");
- cprintf("Store queue size: %i\n", stores);
+ cprintf("Store queue size: %i\n", storeQueue.size());
cprintf("Store queue: ");
for (const auto& e: storeQueue) {
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 19f190b..5b31d20 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -304,7 +304,7 @@
int numLoads() { return loadQueue.size(); }
/** Returns the number of stores in the SQ. */
- int numStores() { return stores; }
+ int numStores() { return storeQueue.size(); }
// hardware transactional memory
int numHtmStarts() const { return htmStarts; }
@@ -334,10 +334,10 @@
bool lqEmpty() const { return loadQueue.size() == 0; }
/** Returns if the SQ is empty. */
- bool sqEmpty() const { return stores == 0; }
+ bool sqEmpty() const { return storeQueue.size() == 0; }
/** Returns the number of instructions in the LSQ. */
- unsigned getCount() { return loadQueue.size() + stores; }
+ unsigned getCount() { return loadQueue.size() + storeQueue.size(); }
/** Returns if there are any stores to writeback. */
bool hasStoresToWB() { return storesToWB; }
@@ -495,8 +495,6 @@
/** Should loads be checked for dependency issues */
bool checkLoads;
- /** The number of store instructions in the SQ. */
- int stores;
/** The number of store instructions in the SQ waiting to writeback. */
int storesToWB;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/50730
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If816c1f03969665010a5bd7e993fe7f87ac4d0a3
Gerrit-Change-Number: 50730
Gerrit-PatchSet: 2
Gerrit-Owner: Tom Rollet <tom.rol...@huawei.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Tom Rollet <tom.rol...@huawei.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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